'I"
5.48 Digital Electronics
14. Tabulate the PLA programmable table for thc four Boolean functions llstcd
below.
Chapter 6
A(x,y, z) ~IIIl(O, 1.2,4,6)
B(x,y,z) ~ L>"(0.2.6, 7)
C(x,y,z) ~ LIII(3.6)
Synchronous Sequential
D(x,y,z) ~ L"I( 1.3.5.7)
logic Circuit
15. Tabulalc lht" PLA programming table for the four Boolean funcliom listed
below. l\'1inillliz,e the number of product terms.
A(x,y,Z) ~ L(1.2.4.6)
B(x,J',z)~ L(O, 1,6,7)
C(x,J',z) ~ L(2,6)
D(x,y,z) ~ L(l,2,3,5, 7)
16. Derive the PLA programming table for the combinational circuit that squares 6.1 Introduction
a 3-bit number. Minimize the number of product terms.
A block diagram of a sequential circuit is shown in Fig.6.1. It consists ~f a combi
17. List the PLA programming table for thc BCD to excess 3 code converter national circuit to which storage elements arc connected to form a feedback path.
whose Boolean functions are simplified. The storage elements are devices capable of storing binary information. This bi
•..1
18. List the PAL programming table for the BCD to excess 3 code converter nary information stored in these elemcnts at <IllY given time define the state of the
(,) whose Boolean functions are simplined. sequential circuit attltm time.
19. The following is a truth table of a 3-input, 4-outP111 combinational circuit.
,I . r-::-:-.-----,
c om~lnalional I
Inputs
" " ' - - - I. Outp t
,. Tabulate the PAL programming table for the circuil and mark the fuse map us
,~·.I ill a PAL diagram. CirCUli I
Inputs Outputs
x y z A n C D Feedback
path
0 0 0 0 1 0 0
0 0 I 1 1 1 I
0 I 0 I 0 I 1
0 I 1 0 1 0 I
Fig 6.1 Block diagram of sequential circuits
I 0 0 I 0 1 a
1 0 I The sequential circuit receives the binary information from external inputs.
0100 1
1 1 0 1 1 I 0 These inputs and the present state of memory clements determine the binary value
of the outputs of the circuit. They also de\~I"Illillc the condilion for changing Ihe
-
1 1 I Oil, I""~
state in memory clelllems. Thus. the m:xl state \ll" l!l(' memory clements is also a
function of the external inpuls and the prCSl.'nl Sl.ltL'.
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, !'i'
6.2 Digital Electronics
Synchronous Sequential Logic Circuit 6.3
6.1.1 Mealy Model Sequential Circuit
Fig 6.2 shows the clocked synchronou.s sequential Mealy machine. The output
Z = !(Q,,)
of mealy n1<lchine is [he function of present inputs and present state (Flip flop
outputs). If X is input. Qil is the present Slate and the next state is Q(n+ I). rhe The difference~ hetween the Moore machine and Mealy machine fire tabulated flS
output of Mealy funclion (Zl i~ given below. follows
'. . ';'~. -
·Z~/(X.Q,,)
S.No. Moore machine ~ ~ Mealy machine
Output J. The output or this machine' lS I'lts output is funclion of presel!,l
l
the func(ion of the present slatc input as well as present state...
only.
Next ~tal" r___~,"5"nl Slale
ln~ul X N~Xl Stal~
Ourpul
Oecodor
2. Input changes do not affecl lhc !IlPU~ changes lIlay ~f[cet the
Decodor
oUlput OutpUl of the circuit
Momory 3. It requires more number of states It requires less nLlmber of stales
r-;=: Comblnal1onal Qn+1
logic clrcult Q" Caml>ln.Uan.1
for implementing same function ror implementing same function
~i
"
!.:
L-j IOQlc cirCUli
,. 6.2 Analysis and Synthesis of Synchronous Sequen
,"
,
\' Fig 6.2 Mealy model sequential circuit
tial Circuits
'., The output of memory element is conneeted to the input of output deeoder nnd
') ,
next st<He decoder circuit The output of memory element is considered as present
, state.
'":
'J "
6.1.2 Moore Model Sequential CircUit
;~) ': I
I':' ,
.,~ )
"
NUl Slate ~resenl s.tale
OUlput
NOXl Sl.1te Cecoder
lputX Oc<;odcr
,-' .i .~'~ Momory
Analysis SyntheSis
r;::::: CombInational Q n4',
..,'
.; Output Procedure Procedure
r
l
L--Ij
logic circuit Cambrn.tlan.1
lOOk: cTrcult
Fig 6.3 Moore model sequential cIrcuit
Fig.6.3 shows (he block diagram of J Moore machine. The output of Moore
machine depends only On the present state. So the output of Moore m,lchine is <1
function of its pres~llt stare (QII). If the input i.'\ X. the next stale is Q(n+ I) and the
p....:sent state is QII' The outpHt of Moore m.achille is represenced mathematically
by
Fig 6.4 Flow chart
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, SynchCOlJOUS ScqtJellliiJ1 Lo,yic Circujl 6.5
6.4 Digiw! EkrlmlliL'.<;
inpOlX, since here are tWO 1 K flip flops whleh have outpU' A and IJ. Therefore the
The behaviour or sequential circuit C~lll be determined from the inputs, Dulpllls ex.citation eq\li.llioll (equation formed for njp flop input)
and slateo[ its nip nop~. The outputs and next state ure botha function nfits inputs
Fol' Flip nop .. A 1/\ = xB r'
and the present stale. The analysi1i of a sequential circuit consists of obtailllng a
KA ~xB ~
stale table or stOlle lliagram fm the time sequencc of inputs, outputs and internal
states. The nnaly:>i:- 01' the cloc~.d segllential circuits can be done by following For fill' ftop - B 1/1 = xA
the procedure as shown in Fig.6.i:-·'The reverse process of analysis is known as
K,,=xA /
synthesis of clocked sequential logic circuit. St l,3 : Next stale equatlun. T.he slalC equations ean be det'iced ,hre"'y from
POl' the analysi" or sec!uenlial circuit, we staft with the logic diagram. The thee logic diag ,,,". Looking-" Fig.65 we can see thai thc
r
si~l\al
fur J Inpul of
excitation equatioll or Boolcnn expression o!" each flip-flop is derived from this Ihe flIp 110p A IS generated by the funclion Ii" and Ihe signal for input K by the
logic diagram Then. ((l ohlain Ihe next state cCJui1tion, we insert lhe cs.citation =
funello Bx. Snbslilu'lug J = Ii" :lnd K B:i IIlto a J K llip 110p cl",,'acreristie
eqLtations into lhe characterisfic Cc]lliltiollS. Th~ output equations can be derived n
from the schematiC We can generate thc slate table lIsing output and next stale equation g'[\'cn by
Q!I+1 = fQn+KQIl
equations.
6.2.1 Analysis of Example Sequential Logic Circuit State equatlon fur nlp flop A
:JT~ -Il
AMI == (lb:)Q!1 + (Bx)Q"
where QII =A J
/' =BxA -'- B.'A
JA Js Oil
B ~ ABx +A(B-')
x I ,11
=ARx+ A (8+ x)
® ®
K, KB as B
=ABx+AB+A.>'
-
=AB+x(A+Alf)
-
(A +AR = A+8)
= ~ IV I I'" _.
s IJ =AB+x(A+B)
== AB+Ax+lh
, A/I-r!
'fi
= Ax and K ~ Ax.
State equalion for flip nop B
Fig 6.5 E~ample or sequential logic circuit Similarly, we can rmd lhe stale equation for llip 1101' R J
Fig, 6.5 ~hows a clocked scqu~iltial circuit. It Iln~ one input variable x, one Therefore the ~lutc equation of flip fillp B is given as
output variable y and two clm:ked JK flip flops. The /lip flops arc labelled as A.
and B and their outputs arc labelled as A and A. Band B respectively. B,,+{ = Ax B+ (A x)1l
Step 1 : Type of circuit =AxS + (A +x)B
The output0') of gi\'cn logic circuit (Fig.a.S) depends on present inpllt and = AxB+AB+ m
also on present state (Flip /lop outputs) of flip flnps, so that lhe given sequential =x(AR + B) -1- AH
logi(,; circuit is Mealy sequential machine.
~ 'CIA + B) +AB
Step 2 : Excitation eqUlltions Nil, \ =.-\ x I 13 x ) .-\8
The excitation cqU<lllUm or Boolean expressinns of /lip Oops A and R arc
oblained. The equation:'. will be in thc fonn or prCsLllt slatc.~ A and Band e:-.h'rnal
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5.48 Digital Electronics
14. Tabulate the PLA programmable table for thc four Boolean functions llstcd
below.
Chapter 6
A(x,y, z) ~IIIl(O, 1.2,4,6)
B(x,y,z) ~ L>"(0.2.6, 7)
C(x,y,z) ~ LIII(3.6)
Synchronous Sequential
D(x,y,z) ~ L"I( 1.3.5.7)
logic Circuit
15. Tabulalc lht" PLA programming table for the four Boolean funcliom listed
below. l\'1inillliz,e the number of product terms.
A(x,y,Z) ~ L(1.2.4.6)
B(x,J',z)~ L(O, 1,6,7)
C(x,J',z) ~ L(2,6)
D(x,y,z) ~ L(l,2,3,5, 7)
16. Derive the PLA programming table for the combinational circuit that squares 6.1 Introduction
a 3-bit number. Minimize the number of product terms.
A block diagram of a sequential circuit is shown in Fig.6.1. It consists ~f a combi
17. List the PLA programming table for thc BCD to excess 3 code converter national circuit to which storage elements arc connected to form a feedback path.
whose Boolean functions are simplified. The storage elements are devices capable of storing binary information. This bi
•..1
18. List the PAL programming table for the BCD to excess 3 code converter nary information stored in these elemcnts at <IllY given time define the state of the
(,) whose Boolean functions are simplined. sequential circuit attltm time.
19. The following is a truth table of a 3-input, 4-outP111 combinational circuit.
,I . r-::-:-.-----,
c om~lnalional I
Inputs
" " ' - - - I. Outp t
,. Tabulate the PAL programming table for the circuil and mark the fuse map us
,~·.I ill a PAL diagram. CirCUli I
Inputs Outputs
x y z A n C D Feedback
path
0 0 0 0 1 0 0
0 0 I 1 1 1 I
0 I 0 I 0 I 1
0 I 1 0 1 0 I
Fig 6.1 Block diagram of sequential circuits
I 0 0 I 0 1 a
1 0 I The sequential circuit receives the binary information from external inputs.
0100 1
1 1 0 1 1 I 0 These inputs and the present state of memory clements determine the binary value
of the outputs of the circuit. They also de\~I"Illillc the condilion for changing Ihe
-
1 1 I Oil, I""~
state in memory clelllems. Thus. the m:xl state \ll" l!l(' memory clements is also a
function of the external inpuls and the prCSl.'nl Sl.ltL'.
www.Jntufastupdates.com 1
, !'i'
6.2 Digital Electronics
Synchronous Sequential Logic Circuit 6.3
6.1.1 Mealy Model Sequential Circuit
Fig 6.2 shows the clocked synchronou.s sequential Mealy machine. The output
Z = !(Q,,)
of mealy n1<lchine is [he function of present inputs and present state (Flip flop
outputs). If X is input. Qil is the present Slate and the next state is Q(n+ I). rhe The difference~ hetween the Moore machine and Mealy machine fire tabulated flS
output of Mealy funclion (Zl i~ given below. follows
'. . ';'~. -
·Z~/(X.Q,,)
S.No. Moore machine ~ ~ Mealy machine
Output J. The output or this machine' lS I'lts output is funclion of presel!,l
l
the func(ion of the present slatc input as well as present state...
only.
Next ~tal" r___~,"5"nl Slale
ln~ul X N~Xl Stal~
Ourpul
Oecodor
2. Input changes do not affecl lhc !IlPU~ changes lIlay ~f[cet the
Decodor
oUlput OutpUl of the circuit
Momory 3. It requires more number of states It requires less nLlmber of stales
r-;=: Comblnal1onal Qn+1
logic clrcult Q" Caml>ln.Uan.1
for implementing same function ror implementing same function
~i
"
!.:
L-j IOQlc cirCUli
,. 6.2 Analysis and Synthesis of Synchronous Sequen
,"
,
\' Fig 6.2 Mealy model sequential circuit
tial Circuits
'., The output of memory element is conneeted to the input of output deeoder nnd
') ,
next st<He decoder circuit The output of memory element is considered as present
, state.
'":
'J "
6.1.2 Moore Model Sequential CircUit
;~) ': I
I':' ,
.,~ )
"
NUl Slate ~resenl s.tale
OUlput
NOXl Sl.1te Cecoder
lputX Oc<;odcr
,-' .i .~'~ Momory
Analysis SyntheSis
r;::::: CombInational Q n4',
..,'
.; Output Procedure Procedure
r
l
L--Ij
logic circuit Cambrn.tlan.1
lOOk: cTrcult
Fig 6.3 Moore model sequential cIrcuit
Fig.6.3 shows (he block diagram of J Moore machine. The output of Moore
machine depends only On the present state. So the output of Moore m,lchine is <1
function of its pres~llt stare (QII). If the input i.'\ X. the next stale is Q(n+ I) and the
p....:sent state is QII' The outpHt of Moore m.achille is represenced mathematically
by
Fig 6.4 Flow chart
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, SynchCOlJOUS ScqtJellliiJ1 Lo,yic Circujl 6.5
6.4 Digiw! EkrlmlliL'.<;
inpOlX, since here are tWO 1 K flip flops whleh have outpU' A and IJ. Therefore the
The behaviour or sequential circuit C~lll be determined from the inputs, Dulpllls ex.citation eq\li.llioll (equation formed for njp flop input)
and slateo[ its nip nop~. The outputs and next state ure botha function nfits inputs
Fol' Flip nop .. A 1/\ = xB r'
and the present stale. The analysi1i of a sequential circuit consists of obtailllng a
KA ~xB ~
stale table or stOlle lliagram fm the time sequencc of inputs, outputs and internal
states. The nnaly:>i:- 01' the cloc~.d segllential circuits can be done by following For fill' ftop - B 1/1 = xA
the procedure as shown in Fig.6.i:-·'The reverse process of analysis is known as
K,,=xA /
synthesis of clocked sequential logic circuit. St l,3 : Next stale equatlun. T.he slalC equations ean be det'iced ,hre"'y from
POl' the analysi" or sec!uenlial circuit, we staft with the logic diagram. The thee logic diag ,,,". Looking-" Fig.65 we can see thai thc
r
si~l\al
fur J Inpul of
excitation equatioll or Boolcnn expression o!" each flip-flop is derived from this Ihe flIp 110p A IS generated by the funclion Ii" and Ihe signal for input K by the
logic diagram Then. ((l ohlain Ihe next state cCJui1tion, we insert lhe cs.citation =
funello Bx. Snbslilu'lug J = Ii" :lnd K B:i IIlto a J K llip 110p cl",,'acreristie
eqLtations into lhe characterisfic Cc]lliltiollS. Th~ output equations can be derived n
from the schematiC We can generate thc slate table lIsing output and next stale equation g'[\'cn by
Q!I+1 = fQn+KQIl
equations.
6.2.1 Analysis of Example Sequential Logic Circuit State equatlon fur nlp flop A
:JT~ -Il
AMI == (lb:)Q!1 + (Bx)Q"
where QII =A J
/' =BxA -'- B.'A
JA Js Oil
B ~ ABx +A(B-')
x I ,11
=ARx+ A (8+ x)
® ®
K, KB as B
=ABx+AB+A.>'
-
=AB+x(A+Alf)
-
(A +AR = A+8)
= ~ IV I I'" _.
s IJ =AB+x(A+B)
== AB+Ax+lh
, A/I-r!
'fi
= Ax and K ~ Ax.
State equalion for flip nop B
Fig 6.5 E~ample or sequential logic circuit Similarly, we can rmd lhe stale equation for llip 1101' R J
Fig, 6.5 ~hows a clocked scqu~iltial circuit. It Iln~ one input variable x, one Therefore the ~lutc equation of flip fillp B is given as
output variable y and two clm:ked JK flip flops. The /lip flops arc labelled as A.
and B and their outputs arc labelled as A and A. Band B respectively. B,,+{ = Ax B+ (A x)1l
Step 1 : Type of circuit =AxS + (A +x)B
The output0') of gi\'cn logic circuit (Fig.a.S) depends on present inpllt and = AxB+AB+ m
also on present state (Flip /lop outputs) of flip flnps, so that lhe given sequential =x(AR + B) -1- AH
logi(,; circuit is Mealy sequential machine.
~ 'CIA + B) +AB
Step 2 : Excitation eqUlltions Nil, \ =.-\ x I 13 x ) .-\8
The excitation cqU<lllUm or Boolean expressinns of /lip Oops A and R arc
oblained. The equation:'. will be in thc fonn or prCsLllt slatc.~ A and Band e:-.h'rnal
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