University of Sunderland
Faculty of Applied Sciences
Department of Computing, Engineering & Technology
ELX304 – Electronic System Design
EXAMINATION
Date: January 2017 Time:
Instructions to Candidates:
Time allowed: 3 hours.
There are SIX questions set and FOUR questions
are to be answered.
This is a closed book Examination.
The use of programmable calculators and
dictionaries is forbidden.
Candidates are required to answer the required
number of questions only. Any additional questions
answered will not be marked.
Students should put a cross through any work that
they do not wish to be marked.
This examination contributes 100% to the overall module mark.
Page 1 of 11
, Q1 Figure Q1 shows the state flow diagram of a sequential system :
0 to A
C 0 F
0 0 1
0 A 1 1 to B
0 1
0 to A
D 0 G
0 0 1
B 1 1 to B
1
0 1
0 to A
E 0 H
0 1 0
1 to B
Figure Q1 : Sequential System
a) Construct its state output table (4 marks)
b) Develop a minimised state output table.
If merges are possible then replace the higher alphabetically
ordered states that you have merged, i.e. if A merges with B
then replace B with A. (4 marks)
c) For the minimised system identify all the state assignment rules
and confirm which rules are not satisfied by the state assignment :
You may ignore any states lost during the minimisation process.
State A B C D E F G H
Q1Q2Q3 000 001 100 101 111 010 110 011
(5 marks)
d) Use the above assignment to develop a JK-type flip-flop solution
to your design for Q1b. You need not sketch the final design. (8 marks)
e) The synchronous circuit of figure Q1 is designed to identify a
feature of a 3-bit sequential input (assuming that the circuit
begins with correct synchronisation) :
i) Identify the data feature detected. (3 marks)
ii) How is synchronisation maintained during operation ? (1 mark)
Page 2 of 11
Faculty of Applied Sciences
Department of Computing, Engineering & Technology
ELX304 – Electronic System Design
EXAMINATION
Date: January 2017 Time:
Instructions to Candidates:
Time allowed: 3 hours.
There are SIX questions set and FOUR questions
are to be answered.
This is a closed book Examination.
The use of programmable calculators and
dictionaries is forbidden.
Candidates are required to answer the required
number of questions only. Any additional questions
answered will not be marked.
Students should put a cross through any work that
they do not wish to be marked.
This examination contributes 100% to the overall module mark.
Page 1 of 11
, Q1 Figure Q1 shows the state flow diagram of a sequential system :
0 to A
C 0 F
0 0 1
0 A 1 1 to B
0 1
0 to A
D 0 G
0 0 1
B 1 1 to B
1
0 1
0 to A
E 0 H
0 1 0
1 to B
Figure Q1 : Sequential System
a) Construct its state output table (4 marks)
b) Develop a minimised state output table.
If merges are possible then replace the higher alphabetically
ordered states that you have merged, i.e. if A merges with B
then replace B with A. (4 marks)
c) For the minimised system identify all the state assignment rules
and confirm which rules are not satisfied by the state assignment :
You may ignore any states lost during the minimisation process.
State A B C D E F G H
Q1Q2Q3 000 001 100 101 111 010 110 011
(5 marks)
d) Use the above assignment to develop a JK-type flip-flop solution
to your design for Q1b. You need not sketch the final design. (8 marks)
e) The synchronous circuit of figure Q1 is designed to identify a
feature of a 3-bit sequential input (assuming that the circuit
begins with correct synchronisation) :
i) Identify the data feature detected. (3 marks)
ii) How is synchronisation maintained during operation ? (1 mark)
Page 2 of 11
