University of Sunderland
Faculty of Applied Sciences
Department of Computing, Engineering & Technology
ELX304 – Electronic System Design
EXAMINATION
Date: September 2017 Time:
Instructions to Candidates:
Time allowed: 3 hours.
There are SIX questions set and FOUR questions
are to be answered.
This is a closed book Examination.
The use of programmable calculators and
dictionaries is forbidden.
Candidates are required to answer the required
number of questions only. Any additional questions
answered will not be marked.
Students should put a cross through any work that
they do not wish to be marked.
This examination contributes 100% to the overall module mark.
Page 1 of 10
, Q1 Figure Q1 shows the state flow diagram of a sequential system designed
to identify the serial input sequence 1010 :
0
0
A 1 B 0 C 1 D 0 E
0
0 0 0 0 1
1 0 1
1
F
1 0
Figure Q1 : Sequence Detection System
a) Construct its state output table (4 marks)
b) Develop a minimised state output table.
If merges are possible then replace the higher alphabetically
ordered states that you have merged, i.e. if A merges with
then replace B with A. (4 marks)
c) For the minimised system identify all the state assignment
rules and confirm which rules are not satisfied by the following
state assignment :
State A B C D E F
Q1Q2Q3 000 001 011 010 111 110
You may ignore any states lost during the minimisation process.
(5 marks)
d) Use the above assignment to develop a JK-type flip-flop
solution to your design for Q1b.
You need not sketch the final design. (8 marks)
e) Modify Figure Q1 so if three consecutive 1’s in the sequence
are detected circuit operation freezes and an alarm output is
generated. (4 marks)
Page 2 of 10
Faculty of Applied Sciences
Department of Computing, Engineering & Technology
ELX304 – Electronic System Design
EXAMINATION
Date: September 2017 Time:
Instructions to Candidates:
Time allowed: 3 hours.
There are SIX questions set and FOUR questions
are to be answered.
This is a closed book Examination.
The use of programmable calculators and
dictionaries is forbidden.
Candidates are required to answer the required
number of questions only. Any additional questions
answered will not be marked.
Students should put a cross through any work that
they do not wish to be marked.
This examination contributes 100% to the overall module mark.
Page 1 of 10
, Q1 Figure Q1 shows the state flow diagram of a sequential system designed
to identify the serial input sequence 1010 :
0
0
A 1 B 0 C 1 D 0 E
0
0 0 0 0 1
1 0 1
1
F
1 0
Figure Q1 : Sequence Detection System
a) Construct its state output table (4 marks)
b) Develop a minimised state output table.
If merges are possible then replace the higher alphabetically
ordered states that you have merged, i.e. if A merges with
then replace B with A. (4 marks)
c) For the minimised system identify all the state assignment
rules and confirm which rules are not satisfied by the following
state assignment :
State A B C D E F
Q1Q2Q3 000 001 011 010 111 110
You may ignore any states lost during the minimisation process.
(5 marks)
d) Use the above assignment to develop a JK-type flip-flop
solution to your design for Q1b.
You need not sketch the final design. (8 marks)
e) Modify Figure Q1 so if three consecutive 1’s in the sequence
are detected circuit operation freezes and an alarm output is
generated. (4 marks)
Page 2 of 10
