CPEN 4700 - Final Exam (Answered) 100%

CPEN 4700 - Final Exam (Answered) 100% Harvard Architecture A type of computer system design in which the CPU uses separate memory interfaces for accessing instructions and data operands Index The portion of a memory address that determine where in cache (in what line) a given main memory address can be mapped MMU A hardware device that handles the details of address translation in a system with virtual memory Key Register In an associative memory, this determines the bit positions where matching is significant Ease of Use An architectural quality attribute that reflects how well a given instruction set architecture supports systems programming SAM This memory organization has variable access time and uses a relative address to locate the next item to be read or written Dirty Bit This is used to indicate that a cache line has been modified since it was loaded from main memory Benchmark A program(s) that are used to compare the performance of various computer systems Segment Fault This happens when a location within a variable-sized region of a program's logical memory is referenced, but it is not currently mapped to a location in physical main memory TLB A type of cache used to hold virtual-to-physical address translation information Transistor This technological development was an important factor in moving from "first-generation" to "second-generation" computers Valid Bit This is used to indicate that a cache line has been properly initialized from main memory This early computer used the stored program concept; its logical design was described in a 1945 report written by John von Neumann EDVAC A computer that used (or will use) an 8-bit microprocessor as its main CPU would most likely have a manufacture date of: 1981 A computer that use (or will use) ferrite core technology in its main memory system would most likely have a manufacture date of: 1965 Which of the following is NOT one of the computer architectural quality factors described in our textbook? Synchronicity User-Friendliness An early computer designed by researchers at Harvard avoided the "von Neumann bottleneck" that was due to which of the following shortcomings of the Princeton machine? Placing code and data in the same memory An early computer designed by researchers at Harvard avoided the "vonNeumann bottleneck" using which of these approaches? Separate memories for instructions and data Which of the following is NOT part of the von Neumann execution cycle as discussed in class? Decode operand register Which of the following would be best suited as a benchmark for applications that work mainly on integer values that are not elements of vectors or arrays? Dhrystones Which of the following cache mapping strategies would be likely to achieve the highest hit ratio given the same program and data set? Fully associative The functionality provided in hardware by a content-addressable memory is most similar to which of the following software concepts? A database query Which of the following cache implementation techniques would keep the contents of main memory synchronized with the contents of the cache? Write-Through Which of these virtual memory techniques uses a table(s) to map the addresses of fixed-size regions of memory Paging and Segmentation & Paging Which of these virtual memory techniques uses a table(s) to map the address of variable-size regions of memory? Segmentation and Segmentation & Paging The first computer sold commercially. Approximately 46 of these machines were sold to the U.S. Census Bureau for data processing UNIVAC 1 A machine that debuted during the third generation of computing; it has been described as the world's first supercomputer CDC 6600 The performance of the DEC VAX 11/780 computer was approximately how many MIPS? 1 MIPS A computer with a CPU clock cycle time of 1.25 ns runs at how many MHz? 800 MHz The _______ ___________ of a storage device refers to the amount of information that can be stored in a given physical space or volume info density The static RAM (SRAM) that is commonly used to construct cache memory in computers is essentially an array of _____________ plus the circuitry used to decode addresses and read and write the information flip-flops The dynamic RAM (DRAM) that is commonly used for main memory in computers is essentially a large array of ________________ plus the circuitry used to decode, read, and write the information. Capacitors A random-access memory that can be accessed by word slice or by bit slice Orthogonal memory The observed property of computer programs and data sets that explains why caching improves memory system performance locality of reference The basic unit of information transfer between a cache and the slower memory that sits behind it line A controller for a four-way set-associative cache that uses a(n) ______ replacement algorithm would replace the line (of the four in question) that has had the fewest hits LFU If a system had an on-chip cache but an off-chip MMU, tags would be part of the _____________ address virtual Argument Register In an associative memory, this holds the value being searched for Physical Address This is what is supplied to the main memory devices to uniquely identify the location of an item being read or written. The memory address that is used to access the main memory hardware Integrated Circuit This technological development was an important factor in moving from "second-generation" to "third-generation" computers Tag The portion of a memory address that determines whether or not the access to that address results in a cache miss Which of the following would be best suited as a benchmark for applications that do mathematical calculations on floating-point numbers that are not elements of vectors or arrays? Whestones Which of the following would be best suited as a benchmark for applications that do mathematical calculations on floating-point numbers that are elements of matrices? Linpack Expandability