WGU C952 - Section 5 Zybook Terms fully
solved
Combinational Element
An operational element, such as an AND gate or an ALU.
State Element
A memory element, such as a register or a memory.
Clocking Methodology
The approach used to determine when data is valid and stable relative to the clock.
Edge-Triggered Clocking
A clocking scheme in which all state changes occur on a clock edge.
Control Signal
A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts
with a data signal, which contains information that is operated on by a functional unit.
Asserted
The signal is logically high or true.
Deasserted
The signal is logically low or false.
Datapath Element
A unit used to operate on or hold data within a processor. In the LEGv8 implementation, the datapath
elements include the instruction and data memories, the register file, the ALU, and adders.
Program Counter (PC)
The register containing the address of the instruction in the program being executed.
Register File
A state element that consists of a set of registers that can be read and written by supplying a register
number to be accessed.
Sign-Extend
To increase the size of a data item by replicating the high-order sign bit of the original data item in the
high-order bits of the larger, destination data item.
Branch Target Address
The address specified in a branch, which becomes the new program counter (PC) if the branch is
taken. In the LEGv8 architecture, the branch target is given by the sum of the offset field of the
instruction and the address of the branch.
, Branch Taken
A branch where the branch condition is satisfied and the program counter (PC) becomes the branch
target. All unconditional branches are taken branches.
Branch Not Taken (Untaken Branch)
A branch where the branch condition is false and the program counter (PC) becomes the address of
the instruction that sequentially follows the branch.
Truth Table
From logic, a representation of a logical operation by listing all the values of the inputs and then in
each case showing what the resulting outputs should be.
Don't-Care Term
An element of a logical function in which the output does not depend on the values of all the inputs.
Don't-care terms may be specified in different ways.
Opcode
The field that denotes the operation and format of an instruction.
Single-Cycle Implementation (single clock cycle implementation)
An implementation in which an instruction is executed in one clock cycle. While easy to understand, it
is too slow to be practical.
Pipelining
An implementation technique in which multiple instructions are overlapped in execution, much like
an assembly line.
Structural Hazard
When a planned instruction cannot execute in the proper clock cycle because the hardware does not
support the combination of instructions that are set to execute.
Data Hazard (Pipeline Data Hazard)
When a planned instruction cannot execute in the proper clock cycle because data that is needed to
execute the instruction are not yet available.
Forwarding (Bypassing)
A method of resolving a data hazard by retrieving the missing data element from internal buffers
rather than waiting for it to arrive from programmer-visible registers or memory.
Load-Use Data Hazard
A specific form of data hazard in which the data being loaded by a load instruction has not yet
become available when it is needed by another instruction.
Pipeline Stall (Bubble)
A stall initiated in order to resolve a hazard.
solved
Combinational Element
An operational element, such as an AND gate or an ALU.
State Element
A memory element, such as a register or a memory.
Clocking Methodology
The approach used to determine when data is valid and stable relative to the clock.
Edge-Triggered Clocking
A clocking scheme in which all state changes occur on a clock edge.
Control Signal
A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts
with a data signal, which contains information that is operated on by a functional unit.
Asserted
The signal is logically high or true.
Deasserted
The signal is logically low or false.
Datapath Element
A unit used to operate on or hold data within a processor. In the LEGv8 implementation, the datapath
elements include the instruction and data memories, the register file, the ALU, and adders.
Program Counter (PC)
The register containing the address of the instruction in the program being executed.
Register File
A state element that consists of a set of registers that can be read and written by supplying a register
number to be accessed.
Sign-Extend
To increase the size of a data item by replicating the high-order sign bit of the original data item in the
high-order bits of the larger, destination data item.
Branch Target Address
The address specified in a branch, which becomes the new program counter (PC) if the branch is
taken. In the LEGv8 architecture, the branch target is given by the sum of the offset field of the
instruction and the address of the branch.
, Branch Taken
A branch where the branch condition is satisfied and the program counter (PC) becomes the branch
target. All unconditional branches are taken branches.
Branch Not Taken (Untaken Branch)
A branch where the branch condition is false and the program counter (PC) becomes the address of
the instruction that sequentially follows the branch.
Truth Table
From logic, a representation of a logical operation by listing all the values of the inputs and then in
each case showing what the resulting outputs should be.
Don't-Care Term
An element of a logical function in which the output does not depend on the values of all the inputs.
Don't-care terms may be specified in different ways.
Opcode
The field that denotes the operation and format of an instruction.
Single-Cycle Implementation (single clock cycle implementation)
An implementation in which an instruction is executed in one clock cycle. While easy to understand, it
is too slow to be practical.
Pipelining
An implementation technique in which multiple instructions are overlapped in execution, much like
an assembly line.
Structural Hazard
When a planned instruction cannot execute in the proper clock cycle because the hardware does not
support the combination of instructions that are set to execute.
Data Hazard (Pipeline Data Hazard)
When a planned instruction cannot execute in the proper clock cycle because data that is needed to
execute the instruction are not yet available.
Forwarding (Bypassing)
A method of resolving a data hazard by retrieving the missing data element from internal buffers
rather than waiting for it to arrive from programmer-visible registers or memory.
Load-Use Data Hazard
A specific form of data hazard in which the data being loaded by a load instruction has not yet
become available when it is needed by another instruction.
Pipeline Stall (Bubble)
A stall initiated in order to resolve a hazard.
