Chapte r 7
Memory and Program mable Logic
7 .1 INTRODUCTION
A memory unit is a device to whic h binary information is transferred for storage and from
which information is retrieved when needed for processi ng. Wh en data processing takes place .
information fro m memory is transferred to se lected re gisters in the processing unit. Interme -
dia te and fina l results obta ined in the processing unit are trans ferred back to be stored in mem-
ory . Binary inform ation recei ved from an input device is stored in memory. and information
transferred to an ou tput device is tak en from memory. A memory unit is a collecti on of cells
capable of s.toring a large quantity of bi nary information.
There are two types of memories that are used in digital systems: random-access memory
(RA\f l and rrad-anly memory ( RO~). RA\t: stores new information for later U~. The Pl'OC\."'iS
of storing new information into memory is referredto as a memory write operation. The proce..s
o f transferri ng the stored info nnation out of memo ry is refe rred to as a memory " ad opera-
tion . RA~ can perform both write and read operations. RO~ can perfonn onl y the read op-
eratio n. Th is means that suitable binary information is alre ady sto red inside memory and can
be retrieved or rea d at any time. However, that information can not be altered by writing .
ROM is a programmable logic device (PLO ). The binary information that is stored within such
a device is specified in some fashio n and then em bedded with in the hard ware in a process is
refe rred to esp rog rumm ing the device. The word "prog ram ming" here refers to a hardw are pro-
cedure which specifi cs the bits that are inserted into the hardw are configuration of the dev ice.
ROM is one example o f a PLO . Other such units are th e pro grammable logi c array (PLA).
programmable array logic (PAL), and the field -programmable gate array (FPGA). A PLO is an
integra ted circuit with intcmallogic gates connected through electronic paths that behave sim-
ilarly to fuse s. In the origi nal state o f the device. all the fuse s are intact. Pro gramming the
de vice Invol ves blo wing those fuse s along the paths th at must be re moved in order to obtain
284
, Section 7.2 Random-Access Memory 285
(a) Conventional symbol (b) Array logicsymbol
FIGURE. 7 .1
Conventional and array logic diagrams for OR gate
the particular contiguration of the desired logic function . In this chapter, we introduce the con-
figuration of PLOs and indicate procedures for their use in the design of digital systems . We
also present CMOS FPGAs, which are configured by downloading a stream of bits into the de-
vice to co nfigure tran smission gates to establish the internal connectivity required by a speci -
fied logic function (combinational or sequential).
A typical Pill may have hundreds to millions of gates interconnected through hundreds to thou-
sands of internal paths. In order to show the internallogic diagram of such a device in a concise
form, it is necessary to employ a special gate symbology applicable to array logic. Figure 7.1 shows
the conventional and array logic symbols for a multiple-input OR gate. Instead of having multi-
ple input lines into the gate. we draw a single line entering the gate. The input lines are drawn per-
pendicular to this single line and are connected to the gate through internal fuses. In a similar
fashion, we can draw the array logic for an AND gate. This type of graphical representation for
the inputs of gates will be used throughout the chapter in array logic diagrams.
7 .2 RANDOM -ACCESS MEMORY
A memory unit is a collection of storage cells. together with associated circuits needed to tran s-
fer information into and out of a device. The architecture of memory is such that information
can be selectiv ely retrieved from any of its intemallccations. The time it takes to tran sfer in-
formation to or from any desired random location is always the same-hence the name random-
access memory, abbreviated RAM. In contrast, the time required to retrieve information that
is stored on magnetic tape depends on the locat ion of the data.
A memory unit stores binary information in groups of bits called WOrt/so A word in memo -
ry is an entity of bits that move in and out of storage as a unit. A memory word is a group of
I 's and D's and may represent a number, an instruct ion , one or more alphanumeric characters.
or any other binary-coded infonnation. Agroup of 8 bits is called a byte. Most computer mem-
ories use word s that are multiples of 8 bits in length. Thu s. a l6·bit word contains two bytes.
and a 32-bit word is made up of four bytes. The capacity of a memory unit is usually stated as
the total number of bytes that the unit can store.
Communication between memory and its environment is achieved through data input and
output lines, address selection lines, and control lines that specify the direct ion of transfer. A
block diagram of a memory unit is shown in Fig. 7.2. The n data input line s provide the infor-
mation to be stored in memory. and the n data output lines supply the information coming out
of memory. The k address lines specify the particular word chosen among the many available.
The two control inputs specify the direction of transfe r desired : The Write input causes bina-
ry data to be transferred into the memory. and the Read input causes binary data to be tran s-
ferred out of memory.
,286 Cha pt er 7 Memory and Programmable logic
II dala input ~
l: addre uees --+
"'rile
IIdala output lines
fiGURE 7.2
Block diagram of a me mory unit
Th e me mor y unit is speci fied by the numb er of words it contains and the number of bits
in eac h word. The address lines select one particul ar word . Each word in me mor} i ~ assigned
an ide ntification num ber. called an add ress. starting fro m 0 up 10 24 - I. wh ere k is the
number of address lin es. The selectio n o f a speci fic wor d inside mem ory is done by apply-
ing the k· bit address to the addre ss lines. An internal decod er accepts this addre ss and opcm
the paths needed to se lect the wo rd spec ified. Mem ori es vary great ly in size and ma y range
from 1.024 wo rds . req uiring an add res s of 10 bits. to 232 words. req uiring 32 addre ss bits. It
is custo mary to refe r to the num ber of words (o r bytes) in mem ory with one o f the lcuers K
(kilo). ~1 (mega). and G (g iga). K is equal to 2 10• 1'.1 is equal to 210• and G is equal to 2:10.
Thus. (HK "" 2 1 6. 2~1 = 21J. and 4G = 232.
Con sider. for example. a memory unit with a capacity of IK words of 16 bits each. Since
I K "" 1.02-t = 210 and 16 bits constitute two byt es. we can say that the me[Jl()f) can accom-
mod ate 2.()..t8 = 2K bytes . Figure 1.3 shows possible contents of the first three and the lao,{
Memory add ress
Binary Decimal !-temol)' coe teet
o 11011010101011101 !
000000<XXl1 tOI01OIli00l IOOI
(lXXXlXlO IO 2 ICXKXl IIOIOlOOO IIO I
Ii
~.
···
-.,
1111111101 l02t 10011lOHl 1OIOl OO
1111111110 1022 10000110100011110 !
1111III III 1023 neunooncoun
flc;, URE 7.3
Contents of. 102-4 x 16 memory
, Section 7.2 Random-Access Memory 287
three words of this memory. Each word contains 16 bits that can be divided into two bytes. The
words are recognized by their decima l address from 0 to 1,023. The equivalent binary address
consists of 10 bits. The first address is specified with ten O's: the last address is specified with
ten ls. because 1.023 in binary is eq ual to 1111111 111.A word in memory is selected by its bi-
nary address. When a word is read or written, the memory operates on all 16 bits as a single unit.
The IK X 16 memor y of Fig. 7.3 has 10 bits in the address and 16 bits in each word. As
another exa mple. a 64K X 10 memo ry will have 16 bits in the addre ss (since 64K = 2 16)
and eac h word will consist of 10 bits. The number of address bits needed in a memory is de-
pende nt on the total number of words that can be stored in the memory and is independent of
the number of bits in each word. The number of bits in the address is determined from the re-
lationship 2* e m. where m is the total number of words and k is the numb er of address bits
needed to satisfy the relationship.
Write and Read Operations
The two oper ations that RAM can perform are the write and read operation s. As alluded to
earlier. the write signal specifies a transfe r-in operation and the read signal specifies a transfer-
out ope ration. On accepting one of these control signals. the internal circuits inside the mem-
ory provide the desired operation.
The steps that must be taken for the purpose of transferring a new word to be stored into
memory are as follows:
l. Appl y the binary address of the desired word to the address lines.
2. Appl y the data bits that must be stored in memo ry to the data input lines.
3. Activate the write input.
The memory unit will then take the bits from the input data lines and store them in the word
spec ified by the address lines.
The steps that must be taken for the purpose of transferri ng a stored word out of memory
are as follows:
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the address
and apply them to the output data lines. The contents of the selected word do not change after
the read operation. i.e.. the word operation is nondestructive.
Commercial memory components available in integrated-circuit chips sometimes provide
the two control inputs for read ing and writing in a somewhat different configuration. Instead
of having separate read and write inputs to control the two operations. most integrated circuits
provide two other control inputs: One input selects the unit and the other determi nes the oper-
ation. The memory operations that result from these control inputs are specified in Table 7.1.
The memory enable (sometimes called the chip select) is used to enable the particular mem-
ory chip in a multichip implementation of a large memo ry. When the memory enable is inac-
tive. the memory chip is not selected and no operation is performe d. When the me mory enable
input is active. the read/w rite input determines the operation to be performed.
Memory and Program mable Logic
7 .1 INTRODUCTION
A memory unit is a device to whic h binary information is transferred for storage and from
which information is retrieved when needed for processi ng. Wh en data processing takes place .
information fro m memory is transferred to se lected re gisters in the processing unit. Interme -
dia te and fina l results obta ined in the processing unit are trans ferred back to be stored in mem-
ory . Binary inform ation recei ved from an input device is stored in memory. and information
transferred to an ou tput device is tak en from memory. A memory unit is a collecti on of cells
capable of s.toring a large quantity of bi nary information.
There are two types of memories that are used in digital systems: random-access memory
(RA\f l and rrad-anly memory ( RO~). RA\t: stores new information for later U~. The Pl'OC\."'iS
of storing new information into memory is referredto as a memory write operation. The proce..s
o f transferri ng the stored info nnation out of memo ry is refe rred to as a memory " ad opera-
tion . RA~ can perform both write and read operations. RO~ can perfonn onl y the read op-
eratio n. Th is means that suitable binary information is alre ady sto red inside memory and can
be retrieved or rea d at any time. However, that information can not be altered by writing .
ROM is a programmable logic device (PLO ). The binary information that is stored within such
a device is specified in some fashio n and then em bedded with in the hard ware in a process is
refe rred to esp rog rumm ing the device. The word "prog ram ming" here refers to a hardw are pro-
cedure which specifi cs the bits that are inserted into the hardw are configuration of the dev ice.
ROM is one example o f a PLO . Other such units are th e pro grammable logi c array (PLA).
programmable array logic (PAL), and the field -programmable gate array (FPGA). A PLO is an
integra ted circuit with intcmallogic gates connected through electronic paths that behave sim-
ilarly to fuse s. In the origi nal state o f the device. all the fuse s are intact. Pro gramming the
de vice Invol ves blo wing those fuse s along the paths th at must be re moved in order to obtain
284
, Section 7.2 Random-Access Memory 285
(a) Conventional symbol (b) Array logicsymbol
FIGURE. 7 .1
Conventional and array logic diagrams for OR gate
the particular contiguration of the desired logic function . In this chapter, we introduce the con-
figuration of PLOs and indicate procedures for their use in the design of digital systems . We
also present CMOS FPGAs, which are configured by downloading a stream of bits into the de-
vice to co nfigure tran smission gates to establish the internal connectivity required by a speci -
fied logic function (combinational or sequential).
A typical Pill may have hundreds to millions of gates interconnected through hundreds to thou-
sands of internal paths. In order to show the internallogic diagram of such a device in a concise
form, it is necessary to employ a special gate symbology applicable to array logic. Figure 7.1 shows
the conventional and array logic symbols for a multiple-input OR gate. Instead of having multi-
ple input lines into the gate. we draw a single line entering the gate. The input lines are drawn per-
pendicular to this single line and are connected to the gate through internal fuses. In a similar
fashion, we can draw the array logic for an AND gate. This type of graphical representation for
the inputs of gates will be used throughout the chapter in array logic diagrams.
7 .2 RANDOM -ACCESS MEMORY
A memory unit is a collection of storage cells. together with associated circuits needed to tran s-
fer information into and out of a device. The architecture of memory is such that information
can be selectiv ely retrieved from any of its intemallccations. The time it takes to tran sfer in-
formation to or from any desired random location is always the same-hence the name random-
access memory, abbreviated RAM. In contrast, the time required to retrieve information that
is stored on magnetic tape depends on the locat ion of the data.
A memory unit stores binary information in groups of bits called WOrt/so A word in memo -
ry is an entity of bits that move in and out of storage as a unit. A memory word is a group of
I 's and D's and may represent a number, an instruct ion , one or more alphanumeric characters.
or any other binary-coded infonnation. Agroup of 8 bits is called a byte. Most computer mem-
ories use word s that are multiples of 8 bits in length. Thu s. a l6·bit word contains two bytes.
and a 32-bit word is made up of four bytes. The capacity of a memory unit is usually stated as
the total number of bytes that the unit can store.
Communication between memory and its environment is achieved through data input and
output lines, address selection lines, and control lines that specify the direct ion of transfer. A
block diagram of a memory unit is shown in Fig. 7.2. The n data input line s provide the infor-
mation to be stored in memory. and the n data output lines supply the information coming out
of memory. The k address lines specify the particular word chosen among the many available.
The two control inputs specify the direction of transfe r desired : The Write input causes bina-
ry data to be transferred into the memory. and the Read input causes binary data to be tran s-
ferred out of memory.
,286 Cha pt er 7 Memory and Programmable logic
II dala input ~
l: addre uees --+
"'rile
IIdala output lines
fiGURE 7.2
Block diagram of a me mory unit
Th e me mor y unit is speci fied by the numb er of words it contains and the number of bits
in eac h word. The address lines select one particul ar word . Each word in me mor} i ~ assigned
an ide ntification num ber. called an add ress. starting fro m 0 up 10 24 - I. wh ere k is the
number of address lin es. The selectio n o f a speci fic wor d inside mem ory is done by apply-
ing the k· bit address to the addre ss lines. An internal decod er accepts this addre ss and opcm
the paths needed to se lect the wo rd spec ified. Mem ori es vary great ly in size and ma y range
from 1.024 wo rds . req uiring an add res s of 10 bits. to 232 words. req uiring 32 addre ss bits. It
is custo mary to refe r to the num ber of words (o r bytes) in mem ory with one o f the lcuers K
(kilo). ~1 (mega). and G (g iga). K is equal to 2 10• 1'.1 is equal to 210• and G is equal to 2:10.
Thus. (HK "" 2 1 6. 2~1 = 21J. and 4G = 232.
Con sider. for example. a memory unit with a capacity of IK words of 16 bits each. Since
I K "" 1.02-t = 210 and 16 bits constitute two byt es. we can say that the me[Jl()f) can accom-
mod ate 2.()..t8 = 2K bytes . Figure 1.3 shows possible contents of the first three and the lao,{
Memory add ress
Binary Decimal !-temol)' coe teet
o 11011010101011101 !
000000<XXl1 tOI01OIli00l IOOI
(lXXXlXlO IO 2 ICXKXl IIOIOlOOO IIO I
Ii
~.
···
-.,
1111111101 l02t 10011lOHl 1OIOl OO
1111111110 1022 10000110100011110 !
1111III III 1023 neunooncoun
flc;, URE 7.3
Contents of. 102-4 x 16 memory
, Section 7.2 Random-Access Memory 287
three words of this memory. Each word contains 16 bits that can be divided into two bytes. The
words are recognized by their decima l address from 0 to 1,023. The equivalent binary address
consists of 10 bits. The first address is specified with ten O's: the last address is specified with
ten ls. because 1.023 in binary is eq ual to 1111111 111.A word in memory is selected by its bi-
nary address. When a word is read or written, the memory operates on all 16 bits as a single unit.
The IK X 16 memor y of Fig. 7.3 has 10 bits in the address and 16 bits in each word. As
another exa mple. a 64K X 10 memo ry will have 16 bits in the addre ss (since 64K = 2 16)
and eac h word will consist of 10 bits. The number of address bits needed in a memory is de-
pende nt on the total number of words that can be stored in the memory and is independent of
the number of bits in each word. The number of bits in the address is determined from the re-
lationship 2* e m. where m is the total number of words and k is the numb er of address bits
needed to satisfy the relationship.
Write and Read Operations
The two oper ations that RAM can perform are the write and read operation s. As alluded to
earlier. the write signal specifies a transfe r-in operation and the read signal specifies a transfer-
out ope ration. On accepting one of these control signals. the internal circuits inside the mem-
ory provide the desired operation.
The steps that must be taken for the purpose of transferring a new word to be stored into
memory are as follows:
l. Appl y the binary address of the desired word to the address lines.
2. Appl y the data bits that must be stored in memo ry to the data input lines.
3. Activate the write input.
The memory unit will then take the bits from the input data lines and store them in the word
spec ified by the address lines.
The steps that must be taken for the purpose of transferri ng a stored word out of memory
are as follows:
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the address
and apply them to the output data lines. The contents of the selected word do not change after
the read operation. i.e.. the word operation is nondestructive.
Commercial memory components available in integrated-circuit chips sometimes provide
the two control inputs for read ing and writing in a somewhat different configuration. Instead
of having separate read and write inputs to control the two operations. most integrated circuits
provide two other control inputs: One input selects the unit and the other determi nes the oper-
ation. The memory operations that result from these control inputs are specified in Table 7.1.
The memory enable (sometimes called the chip select) is used to enable the particular mem-
ory chip in a multichip implementation of a large memo ry. When the memory enable is inac-
tive. the memory chip is not selected and no operation is performe d. When the me mory enable
input is active. the read/w rite input determines the operation to be performed.
