Summary Basic circuits in digital electronics

Experiment 4
MULTIPLEXERS AND DEMULTIPLEXERS
Name: SIBIN THOMAS SISIL
Roll No.: 39


1 Objectives
1. To design and implement a 4 : 1 multiplexer using gates in breadboard,
verilog and mini FPGA.

2. To cascade two 4 : 1 multiplexers to form 8 : 1 multiplexer on mini-
FPGA.

3. To implement 8 : 1 multiplexer using 74150 IC

4. To implement the logic function f(A,B,C) = m(1,3,4,7) using the 8 : 1
multiplexer using breadboard, Verilog and mini FPGA.

5. To implement the logic function f(A,B,C,D) = m(1,4,9,12,14)using the
8 : 1 multiplexer IC 74151.

6. To design and implement a 1 : 4 demultiplexer using gates using
breadboard, Verilog and mini FPGA.

7. To implement 8 : 1 demultiplexer with IC 74138.


2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.

, 2.1 4:1 Multiplexer
A 4:1 multiplexer has four input lines I 0 to I 3 and two select lines X and
Y.For X=0,Y=0 the output is I 0 .For X=0,Y=1 the output is I 1 .For X=1,Y=0
the output is I 2 .For X=1,Y=1 the output is I 3 .
The circuit is shown in Fig. 1.


2.1.1 4:1 Multiplexer with ICs
The wiring diagram is shown in Fig. 2.
The IC is wired and applied various bit patterns to the input pins and
obtained the required output.

2.1.2 4:1 Multiplexer with Verilog and Mini FPGA
The gate level Verilog model for 4:1 Multiplexer is listed in Code 1.
1 // module 4 : 1 MUX
2 module fourtoonemux ( output w i r e y , i n p u t w i r e I0 , I1 , I2 , I3 ,
s0 , s1 , En) ;
3 w i r e s0bar , s1bar , a , b , c , d ;
4 not n1 ( s0bar , s 0 ) ;
5 not n2 ( s1bar , s 1 ) ;
6 and n3 ( a , s0bar , s1bar , I0 , En) ;
7 and n4 ( b , s0 , s1bar , I1 , En) ;
8 and n5 ( c , s0bar , s1 , I2 , En) ;
9 and n6 ( d , s0 , s1 , I3 , En) ;
10 o r n7 ( y , a , b , c , d ) ;
11 endmodule
Listing 1: Verilog code for 4:1 Multiplexer
The code is tested with a mini FPGA and verified the result.

, Figure 1: Circuit of 4:1 Multiplexer




Figure 2: Wiring diagram of 4:1 Multiplexer