Summary flip flops

Experiment 5
FLIP-FLOPS
Name: SIBIN THOMAS SISIL
Roll No.: 39


1 Objectives
1. To implement S-R. J-K, D and T flip-flops using basic gates on both
breadboard and FPGA board
2. To implement the conversions D to T, T to D on mini FPGA with
verilog.
3. To verify the truth tables of J-K, D flip-flops .using flip-flop ICs.


2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.

2.1 S-R FLIP-FLOP
The circuit is shown in Fig. 1.

The truth table of the circuit is shown in Fig. 2.


2.1.1 S-R Flip-flop with ICs
The wiring diagram using IC 7400 is shown in Fig. 3.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 2.

, Figure 1: Circuit of S-R flip-flop




Figure 2: Truth table of S-R flip-flop


2.1.2 S-R Flip-flop with Verilog and Mini FPGA
The gate level Verilog model for S-R Flip-flop is listed in Code 1.
1 // module S−R f l i p −f l o p
2 module s r f f ( output w i r e Q, Qbar , i n p u t w i r e S , R, c l k ) ;
3 w i r e Sbar , Rbar ;
4 nand n1 ( Sbar , S , c l k ) ;
5 nand n2 ( Rbar , R, c l k ) ;
6 nand n3 (Q, Sbar , Qbar ) ;
7 nand n4 ( Qbar , Rbar ,Q) ;
8 endmodule
Listing 1: Verilog module for S-R flip-flop
The code is tested with a mini FPGA and verified the truth table in Fig. 2.

, Figure 3: Wiring diagram of S-R flip-flop


2.2 J-K FLIP-FLOP
The circuit is shown in Fig. 4.

The truth table of the circuit is shown in Fig. 5.


2.2.1 J-K Flip-flop with ICs
The wiring diagram using ICs 7400 and ICs 7410 is shown in Fig. 6.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 5.

2.2.2 J-K Flip-flop with Verilog and Mini FPGA
The gate level Verilog model for J-K Flip-flop is listed in Code 2.
1 // module J−K f l i p −f l o p
2 module JKFF PoS ( q , qbar , j , k , c l k , c l r , pr ) ;
3 output q , qbar :
4 input j , k , clk ;