Summary binary adder circuits

Experiment 2
BINARY ADDER CIRCUITS
Name: SIBIN THOMAS SISIL
Roll No.: 39

1 Objectives
1. To implement half adder on breadboard and mini FPGA and to verify
its truth table.
2. To implement full adder on breadboard and mini FPGA and to verify
its truth table.
3. To implement four bit adder with 7483 IC and mini FPGA


2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.

2.1 Half adder circuit
The truth table is shown in Fig. 1.

The K-maps obtained from the truth table are shown in Fig. 2.

Therefore the logic function for the sum bit and carry bit in half adder is
Sn = X n ⊕ Y n (1)
Cn = Xn · Y n (2)
The circuit is shown in Fig. 3.

, Figure 1: Truth table of halfadder




Figure 2: K-maps of halfadder




Figure 3: Circuit of half adder