Experiment 3
ONE DIGIT BCD ADDER
Name: SIBIN THOMAS SISIL
Roll No.: 39
1 Objectives
1. To design and implement a one digit BCD adder in breadboard, Verilog
and mini FPGA.
2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.
2.1 ONE DIGIT BCD ADDER
• BCD representations for decimals from 0 to 9 (000-1001) are the four
bit representations of their respective binary values.
• The remaining four bit patterns (1010-1111) are invalid.
• The BCD representation of the decimal numbers from 10 to 15 are
obtained by adding binary number 0110 to it.
• The design of the correction circuit is as follows.
• The output of the circuit should be logic high if either the carry output
of the first stage falls in the range from 1010 to 1111.
• The correction factor of 0110 need to be applied when the carry outof
the first adder stage is 1 as well.
, • Therefore the correction logic should be,
Z = C out + S 2 · S 3 + S 3 · S 1 (1)
The truth table of the correction circuit is shown in Fig. 1.
The K-map simplification of the BCD correction circuit is shown in Fig. 2.
2.1.1 One bit BCD adder circuit
The circuit is shown in Fig. 3.
2.1.2 BCD Adder with ICs
The wiring diagram using IC 7483 is shown in Fig. 4.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 1.
2.1.3 Half adder with Verilog and Mini FPGA
The gate level Verilog model for BCD adder is listed in Code 1.It relies on
four bit full adder
1 // module BCD adder
2 ‘ i n c l u d e ” f o u r b i t a d d e r . v”
3 module bcdadder (
4 output [ 3 : 0 ] sum ,
5 output cout ,
6 input [ 3 : 0 ] x ,
7 input [ 3 : 0 ] y ,
8 input cin
9 );
10
11 w i r e c0 , c1 , a , b , c , d ;
12 w i r e [ 3 : 0 ] sum1 ,X;
13 f o u r b i t a d d e r ADD1( sum1 , c0 , x , y , c i n ) ;
14 and n1 ( a , sum1 [ 3 ] , sum1 [ 2 ] ) ;
15 and n2 ( b , sum1 [ 3 ] , sum1 [ 1 ] ) ;
ONE DIGIT BCD ADDER
Name: SIBIN THOMAS SISIL
Roll No.: 39
1 Objectives
1. To design and implement a one digit BCD adder in breadboard, Verilog
and mini FPGA.
2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.
2.1 ONE DIGIT BCD ADDER
• BCD representations for decimals from 0 to 9 (000-1001) are the four
bit representations of their respective binary values.
• The remaining four bit patterns (1010-1111) are invalid.
• The BCD representation of the decimal numbers from 10 to 15 are
obtained by adding binary number 0110 to it.
• The design of the correction circuit is as follows.
• The output of the circuit should be logic high if either the carry output
of the first stage falls in the range from 1010 to 1111.
• The correction factor of 0110 need to be applied when the carry outof
the first adder stage is 1 as well.
, • Therefore the correction logic should be,
Z = C out + S 2 · S 3 + S 3 · S 1 (1)
The truth table of the correction circuit is shown in Fig. 1.
The K-map simplification of the BCD correction circuit is shown in Fig. 2.
2.1.1 One bit BCD adder circuit
The circuit is shown in Fig. 3.
2.1.2 BCD Adder with ICs
The wiring diagram using IC 7483 is shown in Fig. 4.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 1.
2.1.3 Half adder with Verilog and Mini FPGA
The gate level Verilog model for BCD adder is listed in Code 1.It relies on
four bit full adder
1 // module BCD adder
2 ‘ i n c l u d e ” f o u r b i t a d d e r . v”
3 module bcdadder (
4 output [ 3 : 0 ] sum ,
5 output cout ,
6 input [ 3 : 0 ] x ,
7 input [ 3 : 0 ] y ,
8 input cin
9 );
10
11 w i r e c0 , c1 , a , b , c , d ;
12 w i r e [ 3 : 0 ] sum1 ,X;
13 f o u r b i t a d d e r ADD1( sum1 , c0 , x , y , c i n ) ;
14 and n1 ( a , sum1 [ 3 ] , sum1 [ 2 ] ) ;
15 and n2 ( b , sum1 [ 3 ] , sum1 [ 1 ] ) ;
