Summary BASIC GATES IN DIGITAL ELECTRONICS

Experiment 1
Familiarization of Logic Gates with QUCS, ICs
and Mini FPGA Board
Name: SIBIN THOMAS SISIL
Roll No.: 39


1 Objectives
1. To verify the truth tables of AND, OR, NOT, NAND, NOR, EX-OR
and EX-NOR gates with QUCS, discrete ICs and Verilog and mini
FPGA board.

2. To verify the non-associativity and universality of NAND and NOR
gates with QUCS, discrete ICs and Verilog and mini FPGA board.

3. To verify the relation between XOR and XNOR function using QUCS,
discrete ICs, Verilog and mini FPGA boards.


2 Observations
The observations of experiments done on logic gates with QUCS, discrete ICs
and FPGA are detailed below.

2.1 Verification of Truth Tables of Logic Gates with
QUCS
AND Gate The logic function for a two variable AND is

Y =A·B (1)

,where Y is the output and A and B are the inputs. Its output is logic high
when both inputs are high.The output is low when any of the input is low.
The observations are shown in Fig. 1.




A.X B.X Y.X
0000 0 0 0
0001 0 1 0 dtime 0 1n 2n 3n 4n 5n

0010 1 0 0 A.X
B.X
0011 1 1 1
Y.X



(a) QUCS Schematic (b) Truth table of AND (c) Waveforms for AND gate

Figure 1: Simulation of AND Gate with QUCS



OR Gate The logic function for a two variable OR is

Y =A+B (2)

where Y is the output and A and B are the inputs. Its output is logic high
when any of the inputs are high.The output is low when all the inputs are
low. The observations are shown in Fig. 2.




(a) QUCS Schematic (b) Truth table of OR (c) Waveforms for OR gate

Figure 2: Simulation of OR Gate with QUCS

,NOT Gate The logic function for a two variable NOT is

Y = Ā (3)

where Y is the output and A is the inputs. Its output is logic high when the
input is low.The output is low when the input is high. The observations are
shown in Fig. 3.




(a) QUCS Schematic (b) Truth table of (c) Waveforms for NOT gate
NOT

Figure 3: Simulation of NOT Gate with QUCS



NAND Gate The logic function for a two variable NAND is

Y =A·B (4)

where Y is the output and A and B are the inputs. When one of its inputs
is low, the output is high.When both inputs are low, output is high. The
observations are shown in Fig. 4.


NOR Gate The logic function for a two variable NOR is

Y =A+B (5)

where Y is the output and A and B are the inputs. Its output is logic high
when both inputs are low.The output is low when any of the inputS is HIGH.
The observations are shown in Fig. 5.

, (a) QUCS Schematic (b) Truth table of (c) Waveforms for NAND gate
NAND

Figure 4: Simulation of NAND Gate with QUCS


XOR Gate The logic function for a two variable XOR is

Y = A.B̄ + Ā.B = A ⊕ B (6)

where Y is the output and A and B are the inputs. Its output is logic high
when one of the inputs is high and the other is low.The output is low when
the inputs are at the same logic level. Generally, for an n-input XOR function,
the output is high when the parity of the input bit pattern is odd and low
when the parity is even. The observations are shown in Fig. 6.


XNOR Gate The logic function for a two variable XNOR is

Y = A.B + Ā.B̄ = A ⊙ B (7)

where Y is the output and A and B are the inputs. Its output is logic high
when both inputs are high.The output is low when any of the input is low.
The observations are shown in Fig. 7.



2.2 Verification of Truth Tables of Logic Gates with
Discrete ICS
NOT Gate The wiring diagram is shown in Fig. 8.