ARM microarchitecture
how many instructions can be fetched - answers4
What follows the fetch queue - answersARMv8 instruction decode
where do the decoded instructions travel to? - answersthe instruction scheduler
How many execution units? - answers8 - 2 for floating point
2 for integer
1 normal alu
1 for store
2 for load/ store
Registers following execute - answers4 for integer, 4 for floating point. This is written to
data cache
how many cycles are given to floating point calculations? - answers4
What are the registers in Cortex-A53 architecture - answersR0-R12 -> general purpose
R13 -> stack pointer (used by subroutine calls)
R14 -> Link Register (Used by subroutine calls)
R15 -> program counter (points to next instruction to be executed)
CSPR
What is CSPR? - answersCurrent program status register. These are flags used by
conditional branch instructions.
Examples of CSPR flags - answersN ->Negative result from ALU
Z -> Zero result from ALU
how many instructions can be fetched - answers4
What follows the fetch queue - answersARMv8 instruction decode
where do the decoded instructions travel to? - answersthe instruction scheduler
How many execution units? - answers8 - 2 for floating point
2 for integer
1 normal alu
1 for store
2 for load/ store
Registers following execute - answers4 for integer, 4 for floating point. This is written to
data cache
how many cycles are given to floating point calculations? - answers4
What are the registers in Cortex-A53 architecture - answersR0-R12 -> general purpose
R13 -> stack pointer (used by subroutine calls)
R14 -> Link Register (Used by subroutine calls)
R15 -> program counter (points to next instruction to be executed)
CSPR
What is CSPR? - answersCurrent program status register. These are flags used by
conditional branch instructions.
Examples of CSPR flags - answersN ->Negative result from ALU
Z -> Zero result from ALU
