I NV E N TI V E
Universal Verification Methodology
(UVM)
September 2011 – UVM1.1
, UVM Agenda
Introduction to UVM and Coverage Driven Verification
UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary
2
, What is UVM?
UVM is the Universal Verification Methodology
– A methodology and a library that codifies the best practices for
efficient and exhaustive verification.
• A complete, proven solution
– Proven solution, with a success record and large community of users
with methodology knowledge and commitment
– Well-thought-out solution for a wide variety of verification challenges
• Open
– A key motivation for moving to SystemVerilog
– An Accellera standard, supported by Cadence, Mentor and Synopsys
• Enables reuse of verification environments
– Verification IP can dramatically speed-up delivery and improve quality
– A common methodology that also works for other languages
(SystemVerilog, e, SystemC)
3 © 2011 Cadence Design Systems, Inc. All rights reserved.
, UVM is Production Ready
Cadence Verification Methodology Leadership from the Beginning…
2000 eRM Jan
2006URM
2008 OVM Feb 2011 UVM
eVC OVC UVC
Configuration DUT I/F Configuration DUT I/F Configuration DUT I/F
Passive Agent Active Agent Passive Agent Active Agent Passive Agent Active Agent
Sequence_driver Sequencer Sequencer
Monitor Monitor Monitor
Seqs. Seqs. Seqs.
Checks Checks Checks
Coverage BFM Coverage Driver Coverage Driver
OVM 2.1.1
Included: Added: Added:
• Architecture • SystemVerilog support • SV callback enhancements
• Sequences • Architecture • Report catching callback
• Messaging/logging • Sequences • SV end of test enhancements
• Reset/clocking • Factory • Closer to eRM capability
• Common test interface • Configuration mechanism • Register support
• Packaging & code structure • Field automation • Enhanced phasing
Added: • Message macros • Partial TLM2 support
• Module to system reuse • Register pkg (contribution) • Improved configuration and
• Register package (vr_ad) • Integration of AVM base classes command line support
• HW/SW co-verification •TLM Communication Channel • Script for “o” to “u” migration for
• Multi-language interoperability OVM users
4 © 2011 Cadence Design Systems, Inc. All rights reserved.
Universal Verification Methodology
(UVM)
September 2011 – UVM1.1
, UVM Agenda
Introduction to UVM and Coverage Driven Verification
UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary
2
, What is UVM?
UVM is the Universal Verification Methodology
– A methodology and a library that codifies the best practices for
efficient and exhaustive verification.
• A complete, proven solution
– Proven solution, with a success record and large community of users
with methodology knowledge and commitment
– Well-thought-out solution for a wide variety of verification challenges
• Open
– A key motivation for moving to SystemVerilog
– An Accellera standard, supported by Cadence, Mentor and Synopsys
• Enables reuse of verification environments
– Verification IP can dramatically speed-up delivery and improve quality
– A common methodology that also works for other languages
(SystemVerilog, e, SystemC)
3 © 2011 Cadence Design Systems, Inc. All rights reserved.
, UVM is Production Ready
Cadence Verification Methodology Leadership from the Beginning…
2000 eRM Jan
2006URM
2008 OVM Feb 2011 UVM
eVC OVC UVC
Configuration DUT I/F Configuration DUT I/F Configuration DUT I/F
Passive Agent Active Agent Passive Agent Active Agent Passive Agent Active Agent
Sequence_driver Sequencer Sequencer
Monitor Monitor Monitor
Seqs. Seqs. Seqs.
Checks Checks Checks
Coverage BFM Coverage Driver Coverage Driver
OVM 2.1.1
Included: Added: Added:
• Architecture • SystemVerilog support • SV callback enhancements
• Sequences • Architecture • Report catching callback
• Messaging/logging • Sequences • SV end of test enhancements
• Reset/clocking • Factory • Closer to eRM capability
• Common test interface • Configuration mechanism • Register support
• Packaging & code structure • Field automation • Enhanced phasing
Added: • Message macros • Partial TLM2 support
• Module to system reuse • Register pkg (contribution) • Improved configuration and
• Register package (vr_ad) • Integration of AVM base classes command line support
• HW/SW co-verification •TLM Communication Channel • Script for “o” to “u” migration for
• Multi-language interoperability OVM users
4 © 2011 Cadence Design Systems, Inc. All rights reserved.
