WGU C952 Final Exam Computer Architecture
Latest Update 2024-2025 Actual Exam from
Credible Sources with 350 Questions and
Verified Correct Answers Golden Ticket to
Guaranteed A+ Verified by Professor
/0 - CORRECT ANSWER: In C, the two-letter sequence that represents null
used to check whether character is the last char in string
11, 5, 6, 5, 5 = 32 - CORRECT ANSWER: LEGv8 field bits used L --> R = total
opcode, rm (2nd reg), shamt, Rn (first reg), Rd: (destination)
2 ARM processors - CORRECT ANSWER: A5 package has chip containing ____ ____
____.
2 chips - CORRECT ANSWER: iPad2 consists of how many chips?
32 - CORRECT ANSWER: ARMv8 and MIPS have __-bit instructions
63 - CORRECT ANSWER: Of a doubleword's 64 bits, what is the leftmost bit
numbered?
ABI (Application Binary Interface) - CORRECT ANSWER: [the user portion of the
instruction set + the OS interfaces]
defines standard for binary portability across computers
,used by application programmers
accumulator architechture - CORRECT ANSWER: single register architecture
adder - CORRECT ANSWER: subword parallelism takes advantage of byte- and
halfword-sized data bay partitioning this to perform multiple operations in parallel
advance to the next address - CORRECT ANSWER: to increment a pointer to an
integer (add 8 to the pointer address)
Algol - CORRECT ANSWER: was invented as a way to express algorithms more
naturally than its predecessors
algorithm - CORRECT ANSWER: Affects IC, possibly CPI in program performance
IC: determines number of source program instructions executed --> number of
processor instructions executed
CPI: favoring slower or faster instructions
All 0s - CORRECT ANSWER: How is 0 represented in two's complement?
base or displacement addressing mode - CORRECT ANSWER: operand is at the
memory location whose address is the sum of a register and a constant in the
instruction
CBNZ - CORRECT ANSWER: ARM
if( i==0 ) f= g + h
,-----------------
____ X3, Else
ADD ....
B Exit
Else: SUB ....
clock edge - CORRECT ANSWER: DRAMs enable fast access to data by transferring
bits in bursts. Successive bits are transferred on each _______.
clocking methodology - CORRECT ANSWER: defines when signals can be read and
when they can be written; timing
def: the approach used to determine when data is valid and stable relative to the clock
coarse-grained multithreading - CORRECT ANSWER: A version of hardware
multithreading that implies switching between threads only *after significant events*,
such as a last-level cache miss.
Cobol - CORRECT ANSWER: developed for use in business settings
employs English vocabulary and pucntuation
code generator - CORRECT ANSWER: converts the optimized intermediate
representation into a processor's machine instructions
the last compiler phase
coherence - CORRECT ANSWER: memory system behavior that defines *what* values
can be returned by a read
, popular: snooping
combinational element - CORRECT ANSWER: an operational element, such as an AND
gate or an ALU
datapath element whose output values depend only on present input values
Compiler - CORRECT ANSWER: Affects IC, CPI
IC: efficiency of it, translation speed
CPI: varied
consistency - CORRECT ANSWER: memory system behavior that defines *when*
written values will be returned by a read
context switch - CORRECT ANSWER: A changing of the internal state of the processor
to allow a different process to use the processor that includes saving the state needed
to return to the currently executing process.
CPI (clock cycles per instruction) - CORRECT ANSWER: Average number of clock
cycles per instruction for a program or program fragment
CPU execution time - CORRECT ANSWER: Also called CPU time. The actual time the
CPU spends computing for a specific task.
*seconds for the program*
datapath - CORRECT ANSWER: performs arithmetic computations
where data is transformed via computations like addition or subtraction
Latest Update 2024-2025 Actual Exam from
Credible Sources with 350 Questions and
Verified Correct Answers Golden Ticket to
Guaranteed A+ Verified by Professor
/0 - CORRECT ANSWER: In C, the two-letter sequence that represents null
used to check whether character is the last char in string
11, 5, 6, 5, 5 = 32 - CORRECT ANSWER: LEGv8 field bits used L --> R = total
opcode, rm (2nd reg), shamt, Rn (first reg), Rd: (destination)
2 ARM processors - CORRECT ANSWER: A5 package has chip containing ____ ____
____.
2 chips - CORRECT ANSWER: iPad2 consists of how many chips?
32 - CORRECT ANSWER: ARMv8 and MIPS have __-bit instructions
63 - CORRECT ANSWER: Of a doubleword's 64 bits, what is the leftmost bit
numbered?
ABI (Application Binary Interface) - CORRECT ANSWER: [the user portion of the
instruction set + the OS interfaces]
defines standard for binary portability across computers
,used by application programmers
accumulator architechture - CORRECT ANSWER: single register architecture
adder - CORRECT ANSWER: subword parallelism takes advantage of byte- and
halfword-sized data bay partitioning this to perform multiple operations in parallel
advance to the next address - CORRECT ANSWER: to increment a pointer to an
integer (add 8 to the pointer address)
Algol - CORRECT ANSWER: was invented as a way to express algorithms more
naturally than its predecessors
algorithm - CORRECT ANSWER: Affects IC, possibly CPI in program performance
IC: determines number of source program instructions executed --> number of
processor instructions executed
CPI: favoring slower or faster instructions
All 0s - CORRECT ANSWER: How is 0 represented in two's complement?
base or displacement addressing mode - CORRECT ANSWER: operand is at the
memory location whose address is the sum of a register and a constant in the
instruction
CBNZ - CORRECT ANSWER: ARM
if( i==0 ) f= g + h
,-----------------
____ X3, Else
ADD ....
B Exit
Else: SUB ....
clock edge - CORRECT ANSWER: DRAMs enable fast access to data by transferring
bits in bursts. Successive bits are transferred on each _______.
clocking methodology - CORRECT ANSWER: defines when signals can be read and
when they can be written; timing
def: the approach used to determine when data is valid and stable relative to the clock
coarse-grained multithreading - CORRECT ANSWER: A version of hardware
multithreading that implies switching between threads only *after significant events*,
such as a last-level cache miss.
Cobol - CORRECT ANSWER: developed for use in business settings
employs English vocabulary and pucntuation
code generator - CORRECT ANSWER: converts the optimized intermediate
representation into a processor's machine instructions
the last compiler phase
coherence - CORRECT ANSWER: memory system behavior that defines *what* values
can be returned by a read
, popular: snooping
combinational element - CORRECT ANSWER: an operational element, such as an AND
gate or an ALU
datapath element whose output values depend only on present input values
Compiler - CORRECT ANSWER: Affects IC, CPI
IC: efficiency of it, translation speed
CPI: varied
consistency - CORRECT ANSWER: memory system behavior that defines *when*
written values will be returned by a read
context switch - CORRECT ANSWER: A changing of the internal state of the processor
to allow a different process to use the processor that includes saving the state needed
to return to the currently executing process.
CPI (clock cycles per instruction) - CORRECT ANSWER: Average number of clock
cycles per instruction for a program or program fragment
CPU execution time - CORRECT ANSWER: Also called CPU time. The actual time the
CPU spends computing for a specific task.
*seconds for the program*
datapath - CORRECT ANSWER: performs arithmetic computations
where data is transformed via computations like addition or subtraction
