D386 Extensive study guide
1. Functions of CPU: is the primary component of a computer responsible for executing
instructions and performing calculations.
In summary, the CPU acts as the brain of the computer, processing instructions and data to
perform tasks according to the program's logic, while coordinating with other hardware
components to ensure efficient operation.
2. Functions of the CPU
Instruction Fetch: The CPU retrieves program instructions from memory, typically from RAM or
cache, and prepares them for execution.
3. Functions of the CPU
Instruction Decoding: It interprets the fetched instructions, determining the oper- ation to be
performed and identifying the operands involved.
4. Functions of the CPU
Execution: The CPU carries out the instructions by performing arithmetic, logical, or data
movement operations on data stored in its registers or memory.
5. Functions of the CPU
Control: it manages the execution flow of instructions, including branching (condi- tional or
unconditional jumps) and loop control, based on program conditions and control signals.
6. Functions of the CPU
Pipeline Mangement: Modern CPUs often employ pipelining, breaking down in- structions into
smaller stages and executing multiple instructions simultaneously to improve performance.
7. Functions of ALU: is a key component of the CPU responsible for performing arithmetic and
logical operations on binary data.
The ALU is responsible for performing the fundamental arithmetic and logical oper- ations
required for processing data and executing instructions within the CPU
8. Functions of the CPU
Interrupt Handling: It responds to external events, such as I/O operations or hardware interrupts,
by temporarily suspending the current program execution and servicing the interrupt request.
9. Functions of the CPU
Clock Synchronization: The CPU synchronizes its operations with a system clock, ensuring that
instructions are executed at the appropriate timing intervals.
10.Functions of the CPU
Cache Mangement: The CPU interacts with cache memory to store frequently accessed data and
instructions, reducing the time required to fetch them from main memory.
, D386 Extensive study guide
11.Functions of ALU
Arithmetic Operations: The ALU executes arithmetic operations such as addition, subtraction,
multiplication, and division on binary numbers.
12.Functions of ALU
Logical Operations: It performs logical operations such as AND, OR, XOR, and NOT, which
manipulate binary data based on boolean logic.
13.Functions of ALU
Shift and Rotate Operations: The ALU can shift or rotate binary data left or right by a specified
number of bits, which is useful for data manipulation and addressing.
14.Functions of ALU
Comparison Operation: It compares two binary values to determine if they are equal, not equal,
greater than, less than, or other comparison conditions.
15.Functions of ALU
Bitwise Operations: The ALU manipulates individual bits within binary data, allow- ing for bitwise
AND, OR, XOR, and NOT operations.
16.Function of registers: Registers are small, high-speed storage locations within the CPU that
are used to store data temporarily during processing. They play a crucial role in facilitating the
execution of instructions and the manipulation of data.
17.Functions of Registers
Instruction Register: The IR holds the currently fetched instruction from memory. It decodes the
instruction and determines the operation to be performed by the CPU.
18.Functions of Registers
Program Counter: The PC holds the memory address of the next instruction to be fetched and
executed. After each instruction is fetched, the PC is automatically incremented to point to the
next instruction in memory.
19.Functions of Registers
Memory Address Register (MAR): The MAR holds the memory address of the data to be
fetched or stored in memory. It is used during memory read and write operations.
20.Functions of Registers
Memory Data Register (MDR): The MDR holds the data that is currently being transferred between
the CPU and memory. During a memory read operation, data from memory is placed into the
MDR, and during a memory write operation, data from the CPU is placed into the MDR before
being stored in memory.
21.Functions of Registers
Accumulator (ACC): The accumulator is a general-purpose register used to store intermediate
results of arithmetic and logic operations. It is often used as the primary register for arithmetic
operations.
, D386 Extensive study guide
22.Functions of Registers
Index Registers: Index registers are used to hold memory addresses for indexed addressing
modes. They are often used in conjunction with the accumulator to perform calculations or
address calculations in certain instructions.
Data Registers: Data registers are general-purpose
23.Functions of Registers
Data Registers: Data registers are general-purpose registers used to store data temporarily
during processing. They can hold operands, results of calculations, or any other temporary data
needed by the CPU.
24.Functions of Registers
Flag Registers: Flag registers hold status flags that indicate the outcome of arith- metic and logic
operations. Common flags include zero flag (Z), carry flag (C), overflow flag (V), and sign flag
(S), among others. These flags are used to control program flow and make decisions based on
the outcome of operations.
25.Functions of pipelining: Pipelining is a technique used in computer architec- ture to improve
the efficiency of instruction execution by allowing multiple instructions to be processed
simultaneously
26.Functions of pipelining
Instruction Fetch (IF): The pipeline begins with the instruction fetch stage, where the CPU fetches
the next instruction from memory using the program counter (PC). This instruction is then placed
into the instruction register (IR) for decoding.
27.Functions of pipelining
Instruction Decode (ID): In the instruction decode stage, the CPU decodes the fetched instruction
to determine the operation to be performed and the operands involved. This stage also includes
fetching any necessary data from registers or memory.
28.Functions of pipelining
Execution (EX): The execution stage is where the actual operation specified by the instruction is
performed. This could involve arithmetic or logic operations, memory access, or control flow
operations. The ALU (Arithmetic Logic Unit) typically handles the execution of arithmetic and
logic instructions.
29.Functions of pipelining
Memory Access (MEM): If the instruction involves accessing memory, such as loading data from
or storing data to memory, the memory access stage handles this operation. The memory
address register (MAR) is used to specify the memory address, and the memory data register
(MDR) holds the data being transferred between the CPU and memory.
30.Functions of RAM
Write Back (WB): Finally, in the write back stage, the results of the executed
, D386 Extensive study guide
instruction are written back to the appropriate registers or memory locations. This could involve
updating register values, storing data in memory, or setting status flags.
31.Key Functions of Pipelining: is to overlap the execution of multiple instructions so that while
one instruction is being executed, the next instruction can be fetched and decoded, and
subsequent instructions can progress through the pipeline stages. This overlapping of instruction
processing helps to improve the overall throughput and performance of the CPU by reducing idle
time and maximizing resource utiliza- tion.
32.L1 Chache: is a small, high-speed memory unit located directly on the CPU chip.
Overall, L1 cache plays a critical role in improving CPU performance by providing fast access to
frequently accessed data and instructions, thereby reducing the time spent waiting for data
from slower main memory.
33.L1 Cache Location: L1 cache is physically located on the CPU chip itself, making it extremely
fast to access compared to higher-level caches or main memory, which are located off-chip.
34.L1 Cache Purpose: The primary purpose of L1 cache is to store frequently accessed data and
instructions that the CPU needs to execute instructions quickly. By keeping this data close to
the CPU cores, L1 cache helps reduce the time it takes for the CPU to fetch data from the main
memory.
35.L1 Cache Size: L1 cache is relatively small in size compared to higher-level caches,
typically ranging from a few kilobytes to a few megabytes. Due to its proximity to the CPU
cores, L1 cache is designed to be fast and expensive, so its size is limited to keep costs down.
36.L1 Cache Organization: L1 cache is typically organized into separate caches for instructions
(instruction cache) and data (data cache). This separation allows the CPU to fetch instructions
and data simultaneously, improving overall performance.
37.L1 Cache
Access Speed: L1 cache is the fastest cache level in the memory hierarchy, with access times
measured in a few clock cycles. This rapid access speed allows the CPU to quickly retrieve data
and instructions without waiting for slower main memory access.
38.L1 Cache
Cache Coherency: L1 cache is often split into separate caches for each CPU core in multi-core
processors. In such cases, mechanisms are in place to ensure cache coherency, meaning that
each core's L1 cache remains consistent with the shared main memory and other core's caches.
39.L2 Cache: is a secondary cache memory located on the CPU chip or on a separate chip
close to the CPU.
1. Functions of CPU: is the primary component of a computer responsible for executing
instructions and performing calculations.
In summary, the CPU acts as the brain of the computer, processing instructions and data to
perform tasks according to the program's logic, while coordinating with other hardware
components to ensure efficient operation.
2. Functions of the CPU
Instruction Fetch: The CPU retrieves program instructions from memory, typically from RAM or
cache, and prepares them for execution.
3. Functions of the CPU
Instruction Decoding: It interprets the fetched instructions, determining the oper- ation to be
performed and identifying the operands involved.
4. Functions of the CPU
Execution: The CPU carries out the instructions by performing arithmetic, logical, or data
movement operations on data stored in its registers or memory.
5. Functions of the CPU
Control: it manages the execution flow of instructions, including branching (condi- tional or
unconditional jumps) and loop control, based on program conditions and control signals.
6. Functions of the CPU
Pipeline Mangement: Modern CPUs often employ pipelining, breaking down in- structions into
smaller stages and executing multiple instructions simultaneously to improve performance.
7. Functions of ALU: is a key component of the CPU responsible for performing arithmetic and
logical operations on binary data.
The ALU is responsible for performing the fundamental arithmetic and logical oper- ations
required for processing data and executing instructions within the CPU
8. Functions of the CPU
Interrupt Handling: It responds to external events, such as I/O operations or hardware interrupts,
by temporarily suspending the current program execution and servicing the interrupt request.
9. Functions of the CPU
Clock Synchronization: The CPU synchronizes its operations with a system clock, ensuring that
instructions are executed at the appropriate timing intervals.
10.Functions of the CPU
Cache Mangement: The CPU interacts with cache memory to store frequently accessed data and
instructions, reducing the time required to fetch them from main memory.
, D386 Extensive study guide
11.Functions of ALU
Arithmetic Operations: The ALU executes arithmetic operations such as addition, subtraction,
multiplication, and division on binary numbers.
12.Functions of ALU
Logical Operations: It performs logical operations such as AND, OR, XOR, and NOT, which
manipulate binary data based on boolean logic.
13.Functions of ALU
Shift and Rotate Operations: The ALU can shift or rotate binary data left or right by a specified
number of bits, which is useful for data manipulation and addressing.
14.Functions of ALU
Comparison Operation: It compares two binary values to determine if they are equal, not equal,
greater than, less than, or other comparison conditions.
15.Functions of ALU
Bitwise Operations: The ALU manipulates individual bits within binary data, allow- ing for bitwise
AND, OR, XOR, and NOT operations.
16.Function of registers: Registers are small, high-speed storage locations within the CPU that
are used to store data temporarily during processing. They play a crucial role in facilitating the
execution of instructions and the manipulation of data.
17.Functions of Registers
Instruction Register: The IR holds the currently fetched instruction from memory. It decodes the
instruction and determines the operation to be performed by the CPU.
18.Functions of Registers
Program Counter: The PC holds the memory address of the next instruction to be fetched and
executed. After each instruction is fetched, the PC is automatically incremented to point to the
next instruction in memory.
19.Functions of Registers
Memory Address Register (MAR): The MAR holds the memory address of the data to be
fetched or stored in memory. It is used during memory read and write operations.
20.Functions of Registers
Memory Data Register (MDR): The MDR holds the data that is currently being transferred between
the CPU and memory. During a memory read operation, data from memory is placed into the
MDR, and during a memory write operation, data from the CPU is placed into the MDR before
being stored in memory.
21.Functions of Registers
Accumulator (ACC): The accumulator is a general-purpose register used to store intermediate
results of arithmetic and logic operations. It is often used as the primary register for arithmetic
operations.
, D386 Extensive study guide
22.Functions of Registers
Index Registers: Index registers are used to hold memory addresses for indexed addressing
modes. They are often used in conjunction with the accumulator to perform calculations or
address calculations in certain instructions.
Data Registers: Data registers are general-purpose
23.Functions of Registers
Data Registers: Data registers are general-purpose registers used to store data temporarily
during processing. They can hold operands, results of calculations, or any other temporary data
needed by the CPU.
24.Functions of Registers
Flag Registers: Flag registers hold status flags that indicate the outcome of arith- metic and logic
operations. Common flags include zero flag (Z), carry flag (C), overflow flag (V), and sign flag
(S), among others. These flags are used to control program flow and make decisions based on
the outcome of operations.
25.Functions of pipelining: Pipelining is a technique used in computer architec- ture to improve
the efficiency of instruction execution by allowing multiple instructions to be processed
simultaneously
26.Functions of pipelining
Instruction Fetch (IF): The pipeline begins with the instruction fetch stage, where the CPU fetches
the next instruction from memory using the program counter (PC). This instruction is then placed
into the instruction register (IR) for decoding.
27.Functions of pipelining
Instruction Decode (ID): In the instruction decode stage, the CPU decodes the fetched instruction
to determine the operation to be performed and the operands involved. This stage also includes
fetching any necessary data from registers or memory.
28.Functions of pipelining
Execution (EX): The execution stage is where the actual operation specified by the instruction is
performed. This could involve arithmetic or logic operations, memory access, or control flow
operations. The ALU (Arithmetic Logic Unit) typically handles the execution of arithmetic and
logic instructions.
29.Functions of pipelining
Memory Access (MEM): If the instruction involves accessing memory, such as loading data from
or storing data to memory, the memory access stage handles this operation. The memory
address register (MAR) is used to specify the memory address, and the memory data register
(MDR) holds the data being transferred between the CPU and memory.
30.Functions of RAM
Write Back (WB): Finally, in the write back stage, the results of the executed
, D386 Extensive study guide
instruction are written back to the appropriate registers or memory locations. This could involve
updating register values, storing data in memory, or setting status flags.
31.Key Functions of Pipelining: is to overlap the execution of multiple instructions so that while
one instruction is being executed, the next instruction can be fetched and decoded, and
subsequent instructions can progress through the pipeline stages. This overlapping of instruction
processing helps to improve the overall throughput and performance of the CPU by reducing idle
time and maximizing resource utiliza- tion.
32.L1 Chache: is a small, high-speed memory unit located directly on the CPU chip.
Overall, L1 cache plays a critical role in improving CPU performance by providing fast access to
frequently accessed data and instructions, thereby reducing the time spent waiting for data
from slower main memory.
33.L1 Cache Location: L1 cache is physically located on the CPU chip itself, making it extremely
fast to access compared to higher-level caches or main memory, which are located off-chip.
34.L1 Cache Purpose: The primary purpose of L1 cache is to store frequently accessed data and
instructions that the CPU needs to execute instructions quickly. By keeping this data close to
the CPU cores, L1 cache helps reduce the time it takes for the CPU to fetch data from the main
memory.
35.L1 Cache Size: L1 cache is relatively small in size compared to higher-level caches,
typically ranging from a few kilobytes to a few megabytes. Due to its proximity to the CPU
cores, L1 cache is designed to be fast and expensive, so its size is limited to keep costs down.
36.L1 Cache Organization: L1 cache is typically organized into separate caches for instructions
(instruction cache) and data (data cache). This separation allows the CPU to fetch instructions
and data simultaneously, improving overall performance.
37.L1 Cache
Access Speed: L1 cache is the fastest cache level in the memory hierarchy, with access times
measured in a few clock cycles. This rapid access speed allows the CPU to quickly retrieve data
and instructions without waiting for slower main memory access.
38.L1 Cache
Cache Coherency: L1 cache is often split into separate caches for each CPU core in multi-core
processors. In such cases, mechanisms are in place to ensure cache coherency, meaning that
each core's L1 cache remains consistent with the shared main memory and other core's caches.
39.L2 Cache: is a secondary cache memory located on the CPU chip or on a separate chip
close to the CPU.
