UNIT -4 By-
Ms. Nisha Saha
Implementation Technology & Introduction to VHDL Assistant Proffesor
Et&T Dept., LCIT
1.Implementation Technology:
Classifications:
1. PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND
plane and an OR-plane, where both levels are programmable
Example
Let us implement the following Boolean functions using PLA.
A=XY+XZ′
B=XY′+YZ+XZ′
1
,2.PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a
fixed OR-plane
Implement the following Boolean functions using PAL.
A=XY+XZ
B=XY′+YZ
PLA v.s. PAL
1. PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs. ‰
2. Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation
delay. ‰
3. By using fix OR gates, PALs are cheaper and faster than PLAs. ‰
4. Logic expanders increase the flexibilities of PALs, but result in significant propagation delay. ‰
5. PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits. ‰
6. PLAs and PALs are usually referred to as SPLD.
2
,3.SPLD — refers to any type of Simple PLD, usually either a PLA or PAL
4.CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip.
5.FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity.
CPLD Architecture
1. Complex Programmable Logic Device (CPLD) is programmable logic device and can be programmed by
using VHDL. CPLDs are based on EPROM or EEPROM technology. CPLDs are having extended density
than the SPLDs.
2. The concept of CPLDs is to have a few macrocells on a single chip with simple logic paths. CPLDs are
classified depending upon the architecture which gives rise to high speed, detailed timing and simple
software flow
3. . The basic CPLD consists of configurable logic block (CLB) which consists of AND gate arrays and
interconnects. The logic blocks are programmable AND, fixed OR devices.
4. PAL are available in small sizes, equivalent to a few hundred logic gates. CPLD consists of multiple
circuit blocks in chip. The circuit block in CPLD are same as that of PLA or PAL blocks. Figure below
shows the example of a CPLD.
3
, 5. This CPLD has four PAL blocks which are connected interconnection wires. The PAL block is also
connected to a sub-circuit known as I/O block. The I/O block is connected to number of input and output
pins.
6. The PAL block consists of macrocells. The macrocell consists of flip-flop, a multiplexer, and a tri-state
buffer. The flip-flop is used to store the output value produced by the OR gate. The tri-state buffer acts as a
switch. In function block the AND array gets inputs from the I/O blocks and other function blocks. The
product terms are given to fixed OR gates.
7. The outputs of the multiplexor then sent through a clocked flip-flop. The function blocks are designed
similar to PAL architectures. The I/O block is used to drive signals to the pins of the CPLD device. The
CPLD interconnect is a programmable switch matrix. No switch can connect all internal function blocks to
all other function blocks, therefore flexibility is achieved.
Advantages of CPLD :
1) Easy to design : CPLDs gives simple way to implement a designs.
2) Lower cost : CPLDs require low costs due to the feature of re-programmable.
3) Large product profit : CPLDs require very short development cycles because of which products time to
market is faster and generates the profit.
4) Lower board area : CPLDs has high level of integration.
5) Simple design changes due to re-programming.
6) CPLDs are used in wide applications for prototyping small gate arrays
4
Ms. Nisha Saha
Implementation Technology & Introduction to VHDL Assistant Proffesor
Et&T Dept., LCIT
1.Implementation Technology:
Classifications:
1. PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND
plane and an OR-plane, where both levels are programmable
Example
Let us implement the following Boolean functions using PLA.
A=XY+XZ′
B=XY′+YZ+XZ′
1
,2.PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a
fixed OR-plane
Implement the following Boolean functions using PAL.
A=XY+XZ
B=XY′+YZ
PLA v.s. PAL
1. PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs. ‰
2. Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation
delay. ‰
3. By using fix OR gates, PALs are cheaper and faster than PLAs. ‰
4. Logic expanders increase the flexibilities of PALs, but result in significant propagation delay. ‰
5. PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits. ‰
6. PLAs and PALs are usually referred to as SPLD.
2
,3.SPLD — refers to any type of Simple PLD, usually either a PLA or PAL
4.CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip.
5.FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity.
CPLD Architecture
1. Complex Programmable Logic Device (CPLD) is programmable logic device and can be programmed by
using VHDL. CPLDs are based on EPROM or EEPROM technology. CPLDs are having extended density
than the SPLDs.
2. The concept of CPLDs is to have a few macrocells on a single chip with simple logic paths. CPLDs are
classified depending upon the architecture which gives rise to high speed, detailed timing and simple
software flow
3. . The basic CPLD consists of configurable logic block (CLB) which consists of AND gate arrays and
interconnects. The logic blocks are programmable AND, fixed OR devices.
4. PAL are available in small sizes, equivalent to a few hundred logic gates. CPLD consists of multiple
circuit blocks in chip. The circuit block in CPLD are same as that of PLA or PAL blocks. Figure below
shows the example of a CPLD.
3
, 5. This CPLD has four PAL blocks which are connected interconnection wires. The PAL block is also
connected to a sub-circuit known as I/O block. The I/O block is connected to number of input and output
pins.
6. The PAL block consists of macrocells. The macrocell consists of flip-flop, a multiplexer, and a tri-state
buffer. The flip-flop is used to store the output value produced by the OR gate. The tri-state buffer acts as a
switch. In function block the AND array gets inputs from the I/O blocks and other function blocks. The
product terms are given to fixed OR gates.
7. The outputs of the multiplexor then sent through a clocked flip-flop. The function blocks are designed
similar to PAL architectures. The I/O block is used to drive signals to the pins of the CPLD device. The
CPLD interconnect is a programmable switch matrix. No switch can connect all internal function blocks to
all other function blocks, therefore flexibility is achieved.
Advantages of CPLD :
1) Easy to design : CPLDs gives simple way to implement a designs.
2) Lower cost : CPLDs require low costs due to the feature of re-programmable.
3) Large product profit : CPLDs require very short development cycles because of which products time to
market is faster and generates the profit.
4) Lower board area : CPLDs has high level of integration.
5) Simple design changes due to re-programming.
6) CPLDs are used in wide applications for prototyping small gate arrays
4
