Digital Logic
Circuit Analysis and
Design
Second Edition
Problem Solutions Manual
By Victor P. Nelson
Bill D. Carroll
H. Troy Nagle
J. David Irwin
All Supplement Files Download Link at the end of this PDF file.
Part 1: Chapter 5-8: Page 1-173
Part 2: Chapter 1-4: Page 174-392
, Contents
Chapter 1 Number Systems and Digital Codes .......................................... 1
Chapter 2 Logic Circuits and Boolean Algebra ......................................... 27
Chapter 3 Combinational Logic Circuit Design and Analysis ................... 107
Chapter 4 Introduction to Sequential Circuits ....................................... 189
Chapter 5 Synchronous Sequential Circuit Analysis and Design ............. 215
Chapter 6 Asynchronous Sequential Circuit Analysis and Design ........... 265
Chapter 7 Programmable Digital Logic Devices ..................................... 303
Chapter 8 Design of Digital Systems ...................................................... 347
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist.
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
, Digital Logic Circuit Analysis and Design, 2nd Edition
Part 1: Chapter 5-8
Chapter 5 – Synchronous Sequential Circuit Analysis and Design
5.1 For the synchronous sequential circuit of Fig. P5.1, find:
(a) The state table using K-maps and state assignment A ≡ 0, B ≡ 1.
(b) The state diagram.
(c) The timing diagram for an input sequence x = 00100110 and starting state y = 1.
Figure P5.1
215 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
, Digital Logic Circuit Analysis and Design, 2nd Edition
5.2 Derive state diagrams for the Moore and Mealy circuits shown in Figure P5.2(a) and (b), and
then complete the timing diagram for those circuits.
216 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
Circuit Analysis and
Design
Second Edition
Problem Solutions Manual
By Victor P. Nelson
Bill D. Carroll
H. Troy Nagle
J. David Irwin
All Supplement Files Download Link at the end of this PDF file.
Part 1: Chapter 5-8: Page 1-173
Part 2: Chapter 1-4: Page 174-392
, Contents
Chapter 1 Number Systems and Digital Codes .......................................... 1
Chapter 2 Logic Circuits and Boolean Algebra ......................................... 27
Chapter 3 Combinational Logic Circuit Design and Analysis ................... 107
Chapter 4 Introduction to Sequential Circuits ....................................... 189
Chapter 5 Synchronous Sequential Circuit Analysis and Design ............. 215
Chapter 6 Asynchronous Sequential Circuit Analysis and Design ........... 265
Chapter 7 Programmable Digital Logic Devices ..................................... 303
Chapter 8 Design of Digital Systems ...................................................... 347
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist.
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
, Digital Logic Circuit Analysis and Design, 2nd Edition
Part 1: Chapter 5-8
Chapter 5 – Synchronous Sequential Circuit Analysis and Design
5.1 For the synchronous sequential circuit of Fig. P5.1, find:
(a) The state table using K-maps and state assignment A ≡ 0, B ≡ 1.
(b) The state diagram.
(c) The timing diagram for an input sequence x = 00100110 and starting state y = 1.
Figure P5.1
215 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
, Digital Logic Circuit Analysis and Design, 2nd Edition
5.2 Derive state diagrams for the Moore and Mealy circuits shown in Figure P5.2(a) and (b), and
then complete the timing diagram for those circuits.
216 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
