ECSE 324 Final Exam || A+ Verified Solutions.
Cache correct answers Small, high speed, memory storage that frequently access data or
instructions to reduce access time and improve performance. Acts as a bridge between CPU and
main memory.
Pipeline correct answers multiple instruction stages (such as fetch, decode, execute, memory
access, and write-back) are overlapped in execution
Ideal Pipeline correct answers For each clock cycle, a new instruction is started. Moreover, a
single instruction only takes a single cycle in each step
Pipeline Organization (Steps) correct answers 1) Instruction Fetch: Use the Program Counter
(PC) to fetch a new instruction.
2) Instruction Propagation: Instruction-specific information moves with the instruction through
various pipeline stages.
3) Pipeline Registers: Large intermediate buffers (pipeline registers), such as RA, RB, RV, RZ,
IR, and PC-temp, store instruction data, control signals, and intermediate results between stages.
4) Control Signal Handling: Control signals, like multiplexer inputs, are determined during the
decode stage but are applied as needed during subsequent stages.
Types of Hazards correct answers - Structural Hazard
- Data Hazard
- Control Hazard
Structural Hazard correct answers Caused by contention for a shared resource (ie. memory
interface)
Data Hazard correct answers Occur when one instruction must wait for the result of another
Control Hazard correct answers Occur when the pipeline cannot determine the correct instruction
to fetch next due to a branch or jump instructions
Unconditional Branches correct answers An unconditional branch is an instruction in a program
that causes the execution flow to jump to a specified target address, regardless of any condition
or comparison. Unlike conditional branches, which depend on a specific condition being true or
false, an unconditional branch always redirects control to the new location.
Conditional Branches correct answers Must compute the target address and compare registers.
To optimize, use two delay slots (fill in NOPs if not enough instructions to fill slots).
Memory Delays correct answers Slow Memory access can delay instructions in either the Fetch
or Memory stages.
NOP in the assembler correct answers The assembler can optimize NOP instruction lines with
independent instruction lines.
, Forwarding correct answers Forwarding minimizes stalls by providing data early in the pipeline,
rather than waiting for it to be written to the register file
Control Circuitry (pipeline) correct answers Detects the dependencies during the Decode stage
- Interstage buffers carry register identifiers for instructions
- In Cycle 3, control compares the destination register in compute against sources in Decode
- If match, stall.
Who designed the first A-0 Compiler system in 1952? correct answers Grace Hopper
Moores Law correct answers The number of transistors on a single-chip doubles every two years
Harvard Architecture correct answers Instructions and Data are stored in separate memories
Delay of the last bit for a ripple carry adder correct answers for an n-bit number, the last carry bit
has delay n.
Carry Generates (Addition) correct answers Gi = Ai AND Bi
[if it always produces a carry // sum >= 10]
Carry Propagates correct answers Pi = Ai OR Bi
[if it is carries only when there is an input carry // sum < 10]
Key Carry-lookahead Adder Characteristic correct answers the carry dependency between the 1-
bit full adders is removed ==> delay only three gates
Numbers that can't be represented by fixed point representation correct answers Any number
involving fractions whose denominators have prime factors other than 2
Max delay (critical path) for an n-bit array multiplier correct answers ~= 3*n
Propagation Delay with Carry-Save Adder correct answers = 2n
Method of even further optimizing Multiplication with Carry-Save Adders correct answers Insert
a pipeline register between each row in the array so each clock cycle, new data is fed into the
pipeline.
Complexity of Addition Tree Multiplication Reducer correct answers log[reducer] (n)
==> log base whatever the reduce value is of n
Fixed Point Representation correct answers Reserve a fixed number of bits for the integer part,
and the remainder for the fractional part
Limitation of fixed point Representation correct answers Amount of precision after the decimal
is fixed ==> can't represent extremely large/small values
Cache correct answers Small, high speed, memory storage that frequently access data or
instructions to reduce access time and improve performance. Acts as a bridge between CPU and
main memory.
Pipeline correct answers multiple instruction stages (such as fetch, decode, execute, memory
access, and write-back) are overlapped in execution
Ideal Pipeline correct answers For each clock cycle, a new instruction is started. Moreover, a
single instruction only takes a single cycle in each step
Pipeline Organization (Steps) correct answers 1) Instruction Fetch: Use the Program Counter
(PC) to fetch a new instruction.
2) Instruction Propagation: Instruction-specific information moves with the instruction through
various pipeline stages.
3) Pipeline Registers: Large intermediate buffers (pipeline registers), such as RA, RB, RV, RZ,
IR, and PC-temp, store instruction data, control signals, and intermediate results between stages.
4) Control Signal Handling: Control signals, like multiplexer inputs, are determined during the
decode stage but are applied as needed during subsequent stages.
Types of Hazards correct answers - Structural Hazard
- Data Hazard
- Control Hazard
Structural Hazard correct answers Caused by contention for a shared resource (ie. memory
interface)
Data Hazard correct answers Occur when one instruction must wait for the result of another
Control Hazard correct answers Occur when the pipeline cannot determine the correct instruction
to fetch next due to a branch or jump instructions
Unconditional Branches correct answers An unconditional branch is an instruction in a program
that causes the execution flow to jump to a specified target address, regardless of any condition
or comparison. Unlike conditional branches, which depend on a specific condition being true or
false, an unconditional branch always redirects control to the new location.
Conditional Branches correct answers Must compute the target address and compare registers.
To optimize, use two delay slots (fill in NOPs if not enough instructions to fill slots).
Memory Delays correct answers Slow Memory access can delay instructions in either the Fetch
or Memory stages.
NOP in the assembler correct answers The assembler can optimize NOP instruction lines with
independent instruction lines.
, Forwarding correct answers Forwarding minimizes stalls by providing data early in the pipeline,
rather than waiting for it to be written to the register file
Control Circuitry (pipeline) correct answers Detects the dependencies during the Decode stage
- Interstage buffers carry register identifiers for instructions
- In Cycle 3, control compares the destination register in compute against sources in Decode
- If match, stall.
Who designed the first A-0 Compiler system in 1952? correct answers Grace Hopper
Moores Law correct answers The number of transistors on a single-chip doubles every two years
Harvard Architecture correct answers Instructions and Data are stored in separate memories
Delay of the last bit for a ripple carry adder correct answers for an n-bit number, the last carry bit
has delay n.
Carry Generates (Addition) correct answers Gi = Ai AND Bi
[if it always produces a carry // sum >= 10]
Carry Propagates correct answers Pi = Ai OR Bi
[if it is carries only when there is an input carry // sum < 10]
Key Carry-lookahead Adder Characteristic correct answers the carry dependency between the 1-
bit full adders is removed ==> delay only three gates
Numbers that can't be represented by fixed point representation correct answers Any number
involving fractions whose denominators have prime factors other than 2
Max delay (critical path) for an n-bit array multiplier correct answers ~= 3*n
Propagation Delay with Carry-Save Adder correct answers = 2n
Method of even further optimizing Multiplication with Carry-Save Adders correct answers Insert
a pipeline register between each row in the array so each clock cycle, new data is fed into the
pipeline.
Complexity of Addition Tree Multiplication Reducer correct answers log[reducer] (n)
==> log base whatever the reduce value is of n
Fixed Point Representation correct answers Reserve a fixed number of bits for the integer part,
and the remainder for the fractional part
Limitation of fixed point Representation correct answers Amount of precision after the decimal
is fixed ==> can't represent extremely large/small values
