PCB MID-II
6 MARKS
Architecture of 8086 Microprocessor
The 8086 microprocessor is a 16-bit microprocessor developed by Intel. It has a 20-bit address
bus, which allows it to address up to 1MB of memory, and a 16-bit data bus. The architecture
of 8086 is divided into two main units:
1. Bus Interface Unit (BIU):
Responsible for fetching instructions, reading/writing data, and address generation.
Contains:
o Instruction Queue (6 bytes): Pre-fetches instructions to speed up execution
(supports pipelining).
o Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), ES (Extra Segment).
o Instruction Pointer (IP): Holds the address of the next instruction.
o Address Generation Unit: Calculates physical addresses using:
Physical Address = Segment × 10H + Offset
2. Execution Unit (EU):
Executes instructions fetched by the BIU.
Contains:
o Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
o General Purpose Registers: AX, BX, CX, DX (each 16-bit, can be split into 8-
bit parts).
o Pointer and Index Registers: SP, BP, SI, DI (used for stack and memory
operations).
o Flag Register: Indicates the status of the processor (Zero, Carry, Sign, etc.).
o Control Unit: Decodes and executes instructions.
Block Diagram of 8086 Architecture
, Key Features:
Supports pipelining via the instruction queue.
Uses segmented memory model.
Enhances speed through parallelism (EU and BIU work simultaneously).
Characteristics of Digital and Analog Ports
Digital Ports:
Digital ports are used to handle binary data (0 or 1). They work with discrete signals.
6 MARKS
Architecture of 8086 Microprocessor
The 8086 microprocessor is a 16-bit microprocessor developed by Intel. It has a 20-bit address
bus, which allows it to address up to 1MB of memory, and a 16-bit data bus. The architecture
of 8086 is divided into two main units:
1. Bus Interface Unit (BIU):
Responsible for fetching instructions, reading/writing data, and address generation.
Contains:
o Instruction Queue (6 bytes): Pre-fetches instructions to speed up execution
(supports pipelining).
o Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), ES (Extra Segment).
o Instruction Pointer (IP): Holds the address of the next instruction.
o Address Generation Unit: Calculates physical addresses using:
Physical Address = Segment × 10H + Offset
2. Execution Unit (EU):
Executes instructions fetched by the BIU.
Contains:
o Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
o General Purpose Registers: AX, BX, CX, DX (each 16-bit, can be split into 8-
bit parts).
o Pointer and Index Registers: SP, BP, SI, DI (used for stack and memory
operations).
o Flag Register: Indicates the status of the processor (Zero, Carry, Sign, etc.).
o Control Unit: Decodes and executes instructions.
Block Diagram of 8086 Architecture
, Key Features:
Supports pipelining via the instruction queue.
Uses segmented memory model.
Enhances speed through parallelism (EU and BIU work simultaneously).
Characteristics of Digital and Analog Ports
Digital Ports:
Digital ports are used to handle binary data (0 or 1). They work with discrete signals.
