ECSE-325 Digital Systems W2025 Assignment #3 solutions | Answered all correctly | Academic year :| McGILL UNIVERSITY Department of Electrical and Computer Engineering.

COURSE: ECSE – 325 Assignment #3 WINTER 2025
YOUR NAME:
________________________________________________________________________
McGILL UNIVERSITY
Department of Electrical and Computer Engineering

ECSE-325 Digital Systems W2025

Assignment #3 solutions


Question 1: VHDL Design (10 points)

Using a single process block, write a complete VHDL description of a circuit that, on the
rising edge of the clock signal, CLK, parallel reads in three 16-bit signed numbers, A1,
A2, and A3, and outputs, M, the median value of these three numbers, as well as, D, the
difference between the maximum and minimum values. [think about how many bits you
need to represent the output values]




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity median is
Port ( CLK : in STD_LOGIC;
A1, A2, A3 : in SIGNED(15 downto 0);
M : out SIGNED(15 downto 0);
D : out UNSIGNED(15 downto 0)); -- no sign bit
end median;

architecture Q1 of median is

signal tmp_max, tmp_min : SIGNED(15 downto 0);

begin

-- Clock process
process(CLK)
begin
tmp_max <= A1;
M <= A2; -- median value
tmp_min <= A3;
if rising_edge(CLK) then
if (A1 > A2) and (A1 > A3) then

, COURSE: ECSE – 325 Assignment #3 WINTER 2025
YOUR NAME:
________________________________________________________________________
if A3 > A2 then – otherwise keep default
M <= A3;
tmp_min <= A2;
end if;
else if (A2 > A1) and (A2 > A3) then
tmp_max <= A2;
if A3 > A1 then
M <= A3;
tmp_min <= A1;
else
M <= A1;
tmp_min <= A3;
end if;
else – A3 is the max
tmp_max <= A3;
if A2 > A1 then
M <= A2;
tmp_min <= A1;
else
M <= A1;
tmp_min <= A2;
end if;
end if;
D <= unsigned(tmp_max – tmp_min);
end if; -- no carry in or out
end process;
end Q1;

This will take two clock cycles to produce the correct
value for D and will produce the correct value of M in one
clock cycle. You could move the assignment of D outside of
the clocked block, but then D would be the output of a
rather slow combinational logic block instead of a flipflop,
which is bad synchronous system design.