CSE 120 Final Exam (Mr. Goryll)(questions
and answers with all diagrams included)
What is a serial-in serial-out shift register?
Outputs connected to inputs
What is a serial-in parallel-out shift register?
Outputs parallel out
How does a D Flip-Flop work?
When the clock triggers, the value remembered by the flip-flop becomes the value of the D
input (Data) at that instant.
How does a T Flip-Flop Work?
When the clock triggers, the value remembered by the flip-flop either toggles or remains the
same depending on whether the T input (Toggle) is 1 or 0.
How does a J-K Flip-Flop Work?
When the clock triggers, the value remembered by the flip-flop toggles if the J and K inputs are
both 1 and the value remains the same if both are 0; if they are different, then the value
becomes 1 if the J (Jump) input is 1 and 0 if the K (Kill) input is 1.
How does a S-R Flip-Flop Work?
, When the clock triggers, the value remembered by the flip-flop remains unchanged if R and S
are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S input (Set) is 1. The
behavior in unspecified if both inputs are 1. (In Logisim, the value in the flip-flop remains
unchanged.)
How many clock cycles would it take for the first 1 to appear at serial-out for a circuit with 4
serial D Flip-Flops?
Input: 10010
5 Clock Cylces
How would you create a 3:8 Decoder using 2:4 Decoders and no extra gates?
Note: you could make a 4:8 if S1 in first decoder was a variable
How could you create a 2:4 Decoder using s(a,b,c) = Σm(1,2,4,7) and Cout(a,b,c) = Σm(3,5,6,7)
You have two decoders with a not enable and two OR gates
Decode using not on decoders to find the truth table values, top is enabled by a and bottom by
a' because it is not enabled so top is actually a' and bottom is a
Then you the inputs of second most sig bit, b and least sig bit c to find summation
Implement the functionf(x, y, z) = Σm(0, 1, 3, 4, 7) using 2:1 multiplexers.
and answers with all diagrams included)
What is a serial-in serial-out shift register?
Outputs connected to inputs
What is a serial-in parallel-out shift register?
Outputs parallel out
How does a D Flip-Flop work?
When the clock triggers, the value remembered by the flip-flop becomes the value of the D
input (Data) at that instant.
How does a T Flip-Flop Work?
When the clock triggers, the value remembered by the flip-flop either toggles or remains the
same depending on whether the T input (Toggle) is 1 or 0.
How does a J-K Flip-Flop Work?
When the clock triggers, the value remembered by the flip-flop toggles if the J and K inputs are
both 1 and the value remains the same if both are 0; if they are different, then the value
becomes 1 if the J (Jump) input is 1 and 0 if the K (Kill) input is 1.
How does a S-R Flip-Flop Work?
, When the clock triggers, the value remembered by the flip-flop remains unchanged if R and S
are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S input (Set) is 1. The
behavior in unspecified if both inputs are 1. (In Logisim, the value in the flip-flop remains
unchanged.)
How many clock cycles would it take for the first 1 to appear at serial-out for a circuit with 4
serial D Flip-Flops?
Input: 10010
5 Clock Cylces
How would you create a 3:8 Decoder using 2:4 Decoders and no extra gates?
Note: you could make a 4:8 if S1 in first decoder was a variable
How could you create a 2:4 Decoder using s(a,b,c) = Σm(1,2,4,7) and Cout(a,b,c) = Σm(3,5,6,7)
You have two decoders with a not enable and two OR gates
Decode using not on decoders to find the truth table values, top is enabled by a and bottom by
a' because it is not enabled so top is actually a' and bottom is a
Then you the inputs of second most sig bit, b and least sig bit c to find summation
Implement the functionf(x, y, z) = Σm(0, 1, 3, 4, 7) using 2:1 multiplexers.
