Literally all of CSE120 With 100% correct
answers ( graded A+ )
The RISC-V ISA we discussed uses 32 general-purpose registers. Assume we want to increase the
number of registers to 128. To enable this, the machine instruction format of three operand
instructions would need to be increased by how many bits? - answer 9
128
6 CORRECT
3
Which entity translates assembly code into machine code - answer Assembler CORRECT
Compiler
Linker
Interpreter
What is the purpose of the instruction decode (ID) stage in the 5-stage pipeline discussed in
class? - answer Write Register File
Update PC
All three above
Read Register File CORRECT
A 40GHz processor has a cycle time of - answer 25s CORRECT
40ns
0.25ns
250ps
Consider the code snippet below. In which memory segment does the variable x reside?
,int x = 8;
int main() {
int y[64];
return 1;
} - answer Text
Stack
Static Data CORRECT
Heap
Assume the following topdown profile for an application:
frontend-bound: 20%
backend-bound: 30%
bad-speculation: 10%
retiring: 40%
The application has an average CPI of 5. What is the maximum CPI that can be achieved on that
system? - answer 4
2 CORRECT
5
1
Consider the code snippet below. In which memory segment does the array y reside?
int x = 8;
int main() {
int y[64];
,return 1;
} - answer Static Data
Text
Heap
Stack CORRECT
slli x1, x1, 5 performs the following operation on the value in x1 - answer Multiplication by 32
CORRECT
Multiplication by 64
Division by 32
Division by 5
Assume a 5-stage pipelined processor with the components and latencies above. What is the
minimum clock period (in ps)? - answer 250
Assume a 5-stage pipelined processor with the components and latencies above. Assume that it
is clocked at maximum frequency. What is the total latency of a load instruction (in ps)? -
answer 1250
Assume a single-cycle (single stage) processor with the components and latencies above. What
is the latency of a load instruction (in ps)? - answer 750
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x1, x4
add x1, x3, x3
, add x4, x1, x4 - answer 2
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x1, x2
add x3, x3, x3
add x4, x2, x3 - answer 3
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x2, x3
add x3, x3, x3
add x4, x5, x3 - answer 1
Splitting Caches - answer -Most chips have separate caches for instructions and data
-Often noted ad $I and $D or I-cache and D-cache
-L1 cache is the one closest to CPU
-Advantages
-Extra access port, bandwidth
-Low hit time
-Customize to specific patterns (e.g. line size)
answers ( graded A+ )
The RISC-V ISA we discussed uses 32 general-purpose registers. Assume we want to increase the
number of registers to 128. To enable this, the machine instruction format of three operand
instructions would need to be increased by how many bits? - answer 9
128
6 CORRECT
3
Which entity translates assembly code into machine code - answer Assembler CORRECT
Compiler
Linker
Interpreter
What is the purpose of the instruction decode (ID) stage in the 5-stage pipeline discussed in
class? - answer Write Register File
Update PC
All three above
Read Register File CORRECT
A 40GHz processor has a cycle time of - answer 25s CORRECT
40ns
0.25ns
250ps
Consider the code snippet below. In which memory segment does the variable x reside?
,int x = 8;
int main() {
int y[64];
return 1;
} - answer Text
Stack
Static Data CORRECT
Heap
Assume the following topdown profile for an application:
frontend-bound: 20%
backend-bound: 30%
bad-speculation: 10%
retiring: 40%
The application has an average CPI of 5. What is the maximum CPI that can be achieved on that
system? - answer 4
2 CORRECT
5
1
Consider the code snippet below. In which memory segment does the array y reside?
int x = 8;
int main() {
int y[64];
,return 1;
} - answer Static Data
Text
Heap
Stack CORRECT
slli x1, x1, 5 performs the following operation on the value in x1 - answer Multiplication by 32
CORRECT
Multiplication by 64
Division by 32
Division by 5
Assume a 5-stage pipelined processor with the components and latencies above. What is the
minimum clock period (in ps)? - answer 250
Assume a 5-stage pipelined processor with the components and latencies above. Assume that it
is clocked at maximum frequency. What is the total latency of a load instruction (in ps)? -
answer 1250
Assume a single-cycle (single stage) processor with the components and latencies above. What
is the latency of a load instruction (in ps)? - answer 750
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x1, x4
add x1, x3, x3
, add x4, x1, x4 - answer 2
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x1, x2
add x3, x3, x3
add x4, x2, x3 - answer 3
Assume the following instruction sequence. How many RAW dependencies can be observed in
the sequence?
add x1, x2, x3
mul x2, x2, x3
add x3, x3, x3
add x4, x5, x3 - answer 1
Splitting Caches - answer -Most chips have separate caches for instructions and data
-Often noted ad $I and $D or I-cache and D-cache
-L1 cache is the one closest to CPU
-Advantages
-Extra access port, bandwidth
-Low hit time
-Customize to specific patterns (e.g. line size)
