Computer Organization and Architecture
The following table reflects the memory contents of a part of memory in a one-address machine with an
accumulator:
Address Contents
00 20
20 30
30 40
40 50
50 60
60 70
What values do the following instructions load into the accumulator?
LOAD IMMEDIATE 20
LOAD DIRECT 20
LOAD INDIRECT 20 - (correct Answer) - LOAD IMMEDIATE 20:
Immediate addressing.
The value to be used forms part of the instruction.
In this instance, the value 20 will be loaded into the accumulator.
LOAD DIRECT 20:
Direct addressing.
The instruction contains the address where the value is to found.
Address 20 contains the value 30, thus the value 30 will be loaded into the accumulator
,LOAD INDIRECT 20:
Indirect addressing.
The instruction contains the address where the address of the value to be used, is to be found.
Address 20 contains the address of the value to be used, ie address 30.
Address 30 contains 40, thus the value 40 will be loaded into the accumulator.
Give examples of Intel x86 instructions in which the following addressing modes are used:
Immediate addressing
Direct addressing
Stack addressing
Indexed addressing
Base-addressing
Register indirect addressing - (correct Answer) - Immediate addressing: mov ax,23
Direct addressing: mov ax,[a]
Stack addressing: push ax (pop ax)
Indexed addressing:
mov ax,[si] (mov [di],ax)
Base-addressing:
mov ax,[bp] (mov ax,[bx])
Register indirect addressing:
mov ax,[bx]
, Briefly discuss the concepts of (i) error correcting-codes and (ii) error-detecting codes. - (correct Answer)
- Error detection and correction are techniques that enable reliable delivery of digital data over
unreliable communication channels. Many communication channels are subject to channel noise, and
thus errors may be introduced during transmission from
the source to a receiver. Error detection techniques allow detecting such errors, while error correction
enables reconstruction of the original data in many cases.
What is the distinction between spatial locality and temporal locality? - (correct Answer) - Spatial
locality:
refers to the tendency of execution to involve a number of clustered memory locations.
Temporal locality:
refers to the tendency for a processor to access memorylocations that have been used recently, eg
when a loop is executed, theprocessor executes the same instructions repeatedly.
Briefly describe the cache organisation of the Pentium - (correct Answer) - L1 instruction cache (on-chip):
12K in size and holds micro-operations. Sits
between the instruction decode logic and the execution core.
- L1 data cache (on-chip): 16Kb, 4-way set-associative organisation. Uses a writeback
policy.
- L2 cache of 256Kb: Feeds both L1 data and instruction caches. Its organisation is
(8- way set-associative).
- L3 cache: on-chip (8-way set-associative).
The Memory subsystem contains both the L2 and L3 caches and the system
bus. The bus is used to access main memory when the L1 and L2 caches have a
cache miss.
Explain why one type of RAM is considered to be analog and the other digital. - (correct Answer) - A
DRAM cell is essentially used for main memory and it is an analog device using a capacitor;the capacitor
can store any charge value within a range; a threshold value determines whether the charge is
The following table reflects the memory contents of a part of memory in a one-address machine with an
accumulator:
Address Contents
00 20
20 30
30 40
40 50
50 60
60 70
What values do the following instructions load into the accumulator?
LOAD IMMEDIATE 20
LOAD DIRECT 20
LOAD INDIRECT 20 - (correct Answer) - LOAD IMMEDIATE 20:
Immediate addressing.
The value to be used forms part of the instruction.
In this instance, the value 20 will be loaded into the accumulator.
LOAD DIRECT 20:
Direct addressing.
The instruction contains the address where the value is to found.
Address 20 contains the value 30, thus the value 30 will be loaded into the accumulator
,LOAD INDIRECT 20:
Indirect addressing.
The instruction contains the address where the address of the value to be used, is to be found.
Address 20 contains the address of the value to be used, ie address 30.
Address 30 contains 40, thus the value 40 will be loaded into the accumulator.
Give examples of Intel x86 instructions in which the following addressing modes are used:
Immediate addressing
Direct addressing
Stack addressing
Indexed addressing
Base-addressing
Register indirect addressing - (correct Answer) - Immediate addressing: mov ax,23
Direct addressing: mov ax,[a]
Stack addressing: push ax (pop ax)
Indexed addressing:
mov ax,[si] (mov [di],ax)
Base-addressing:
mov ax,[bp] (mov ax,[bx])
Register indirect addressing:
mov ax,[bx]
, Briefly discuss the concepts of (i) error correcting-codes and (ii) error-detecting codes. - (correct Answer)
- Error detection and correction are techniques that enable reliable delivery of digital data over
unreliable communication channels. Many communication channels are subject to channel noise, and
thus errors may be introduced during transmission from
the source to a receiver. Error detection techniques allow detecting such errors, while error correction
enables reconstruction of the original data in many cases.
What is the distinction between spatial locality and temporal locality? - (correct Answer) - Spatial
locality:
refers to the tendency of execution to involve a number of clustered memory locations.
Temporal locality:
refers to the tendency for a processor to access memorylocations that have been used recently, eg
when a loop is executed, theprocessor executes the same instructions repeatedly.
Briefly describe the cache organisation of the Pentium - (correct Answer) - L1 instruction cache (on-chip):
12K in size and holds micro-operations. Sits
between the instruction decode logic and the execution core.
- L1 data cache (on-chip): 16Kb, 4-way set-associative organisation. Uses a writeback
policy.
- L2 cache of 256Kb: Feeds both L1 data and instruction caches. Its organisation is
(8- way set-associative).
- L3 cache: on-chip (8-way set-associative).
The Memory subsystem contains both the L2 and L3 caches and the system
bus. The bus is used to access main memory when the L1 and L2 caches have a
cache miss.
Explain why one type of RAM is considered to be analog and the other digital. - (correct Answer) - A
DRAM cell is essentially used for main memory and it is an analog device using a capacitor;the capacitor
can store any charge value within a range; a threshold value determines whether the charge is
