CEA 201 FE Exam
CEA 201 FE EXAM NEWEST 2025/2026 COMPLETE ALL QUESTIONS
AND CORRECT DETAILED ANSWERS (VERIFIED ANSWERS) |ALREADY
GRADED A+||BRAND NEW VERSION!
The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter - ANSWER-D
The _________ contains a word of data to be written to memory or the word
most recently read.
A. MAR
B. PC
C. MBR
D. IR - ANSWER-C
The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction - ANSWER-A
_________ is a pipeline hazard.
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, CEA 201 FE Exam
A. Control
B. Resource
C. Data
D. All of the above - ANSWER-D
A ________ hazard occurs when there is a conflict in the access of an operand
location.
A. resource
B. data
C. structural
D. control - ANSWER-B
A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions
in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction - ANSWER-A
The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
A. dynamic branch
B. loop table
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, CEA 201 FE Exam
C. branch history table
D. flag - ANSWER-C
The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back - ANSWER-B
________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag - ANSWER-C
The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7 - ANSWER-D
The OS usually runs in ________.
A. supervisor mode
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, CEA 201 FE Exam
B. abort mode
C. undefined mode
D. fast interrupt mode - ANSWER-A
Microprogramming eases the task of designing and implementing the control unit
and provides support for the family concept.
a. True
b. False - ANSWER-True
Pipelining is a means of introducing parallelism into the essentially sequential
nature of a machine-instruction program.
a. True
b. False - ANSWER-True
The major cost in the life cycle of a system is hardware.
a. True
b. False - ANSWER-False
It is common for programs, both system and application, to continue to exhibit
new bugs after years of operation.
a. True
b. False - ANSWER-True
Procedure calls and returns are not important aspects of HLL programs.
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CEA 201 FE EXAM NEWEST 2025/2026 COMPLETE ALL QUESTIONS
AND CORRECT DETAILED ANSWERS (VERIFIED ANSWERS) |ALREADY
GRADED A+||BRAND NEW VERSION!
The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter - ANSWER-D
The _________ contains a word of data to be written to memory or the word
most recently read.
A. MAR
B. PC
C. MBR
D. IR - ANSWER-C
The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction - ANSWER-A
_________ is a pipeline hazard.
1|Page
, CEA 201 FE Exam
A. Control
B. Resource
C. Data
D. All of the above - ANSWER-D
A ________ hazard occurs when there is a conflict in the access of an operand
location.
A. resource
B. data
C. structural
D. control - ANSWER-B
A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions
in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction - ANSWER-A
The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
A. dynamic branch
B. loop table
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, CEA 201 FE Exam
C. branch history table
D. flag - ANSWER-C
The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back - ANSWER-B
________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag - ANSWER-C
The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7 - ANSWER-D
The OS usually runs in ________.
A. supervisor mode
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, CEA 201 FE Exam
B. abort mode
C. undefined mode
D. fast interrupt mode - ANSWER-A
Microprogramming eases the task of designing and implementing the control unit
and provides support for the family concept.
a. True
b. False - ANSWER-True
Pipelining is a means of introducing parallelism into the essentially sequential
nature of a machine-instruction program.
a. True
b. False - ANSWER-True
The major cost in the life cycle of a system is hardware.
a. True
b. False - ANSWER-False
It is common for programs, both system and application, to continue to exhibit
new bugs after years of operation.
a. True
b. False - ANSWER-True
Procedure calls and returns are not important aspects of HLL programs.
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