Registers and Counters
Registers – is a group of memory elements that work together as a unit.
Buffer register:
Binary word – 2 or more binary,
Binary bit – 1 or 0 bit
Controlled Buffer Register
If CLR = 1 the buffer register is new, ready to received information
If LOAD = 0 , the output from the previews will still remain or OUTPUT IS NC (No change)
, Flip-Flop – is a memory element that stores binary digit as a lower high voltage. It has two stable states;
it remains in of these states until triggered into the other state.
RS. FLIP-FLOP – first flip flops
TRUTH TABLE
R S Q Q
0 0 NO CHANGE
0 1 1 0
1 0 0 1
1 1 RACE
Note: RACE Condition is prohibited because it leads to unpredictable operations.
RS NOR LATCH
S Q
R
Q
R Q
Q
S
Timing Diagram:
1
R
0
1
S
0
1
Q
0
1
Q
0
, D – Flip Flop: is the improve version of RS Flip flop, placing an inverter
S Q D Q
R Q Q
TRUTH TABLE
D Q
0 0
1 1
Timing Diagram:
1
D
0
1
Q
0
Registers – is a group of memory elements that work together as a unit.
Buffer register:
Binary word – 2 or more binary,
Binary bit – 1 or 0 bit
Controlled Buffer Register
If CLR = 1 the buffer register is new, ready to received information
If LOAD = 0 , the output from the previews will still remain or OUTPUT IS NC (No change)
, Flip-Flop – is a memory element that stores binary digit as a lower high voltage. It has two stable states;
it remains in of these states until triggered into the other state.
RS. FLIP-FLOP – first flip flops
TRUTH TABLE
R S Q Q
0 0 NO CHANGE
0 1 1 0
1 0 0 1
1 1 RACE
Note: RACE Condition is prohibited because it leads to unpredictable operations.
RS NOR LATCH
S Q
R
Q
R Q
Q
S
Timing Diagram:
1
R
0
1
S
0
1
Q
0
1
Q
0
, D – Flip Flop: is the improve version of RS Flip flop, placing an inverter
S Q D Q
R Q Q
TRUTH TABLE
D Q
0 0
1 1
Timing Diagram:
1
D
0
1
Q
0
