ELEC 3500 Winter LAB: 2 Combinational CMOS Logic

ELEC 3500 Winter 2017-2018
LAB: 2
Combinational CMOS Logic
Submitted by: Miranda Heredia, 100996160
Joyce Ibrahim, 100997397
Date lab performed: Monday, January 29, 2018
Section: B2
Group: 14

, Q1:
1 – Will work well since the PMOS circuit is pull up and the NMOS is pull down.
2 – Will not work. It does not have an inverting structure since when the input is 1 the NMOS transistor is
turned on which would cause the output to be 1 and pull up.
3 – Will work poorly
4 – Will not work
Q2:




Figure 1: Circuit (A) & (B) Output Waveforms

The red line represents circuit (A), which does work properly as an inverter. One can see that circuit (A)’s
output waveform goes all the way to 2.5 V and goes as low to 0 V, proving it works as an inverter. Circuit
(B)’s output waveform demonstrates that it does not reach 2.5 V and does not swing down to 0 V neither,
thus proving it is not an inverter.
Q3:




Figure 2: Circuit (A) Output Waveform