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ELEC 3908 Winter 2024 LAB # 3 MOSFET Square Law Parameter Extraction and SPICE Model Simulation

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ELEC 3908 Winter 2024 LAB # 3 MOSFET Square Law Parameter Extraction and SPICE Model Simulation

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ELEC 3908 Winter 2024
LAB # 3
MOSFET Square Law Parameter Extraction and SPICE Model
Simulation
Submitted by: Nathan Chen, 101142799
Partner: Omer Cebi
Date lab performed: Thursday April 4th, 2024
Section: B1
Group: Lab group 5




Carleton University
Ottawa, Ontario Canada

, Introduction

This lab aims to study the intricacies of Metal-Oxide Semiconductor Field Effect Transistors
(MOSFETs), focusing on an n-channel MOSFET housed within a CD4007 Dual Inline Package IC chip.
Our analysis aimed to derive parameters for the square law model—a fundamental framework for
comprehending semiconductor dynamics in the realms of physics and electronic engineering. Central to our
investigation were the three principal operating states of a MOSFET: cutoff, triode, and saturation. Through
meticulous observation of how these states fluctuate with variations in gate, drain, and source voltages, we
gained insights into MOSFET behavior across diverse scenarios. Data collection was performed using IC-
CAP software, with subsequent exportation to Excel for extended analysis beyond the laboratory
environment. Further, we utilized SPICE simulation software to juxtapose our empirical findings against
theoretical predictions, adjusting variables such as unbiased threshold voltage, voltage modulation, and
channel length modulation parameters. Our goal was to refine these parameters to enhance the congruence
between simulated outcomes and actual measurements. The ensuing analysis of these simulated
representations offered deeper understanding and validation of our experimental results.

Theory:

A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) operates as a transconductance
device, formed by layering an insulating oxide atop a doped semiconductor substrate, with a conductive
gate of aluminum or polycrystalline Silicon positioned above. The source and drain regions, diffused on
either side of the gate and opposite in type to the substrate, alongside the gate, define the transistor's
dimensions. The MOSFET enables current flow between the source and drain when a conductive channel
forms under the gate, influenced by an appropriate gate potential. This potential attracts minority carriers
(electrons in p-type substrates for n-channel devices, holes in n-type for p-channel devices) to the substrate's
surface, establishing the conductive path.


MOSFETs feature three operational modes: cutoff, triode, and saturation. In cutoff, insufficient
gate-to-source voltage prevents current flow as the electron path doesn't form. The triode mode sees current
as a function of both gate-to-source and drain-to-source voltages until it reaches a saturation voltage,
beyond which the device operates in the saturation region, with current primarily dependent on the gate-to-
source voltage. This stage exhibits channel length modulation, a minor dependence on the drain-to-source
voltage, accentuated in devices with shorter channels due to the significant intrusion of the drain depletion
region.
The "square-law" model simplifies the drain current equation by relating the charge under the gate
to the bias and integrating this across the channel. In this model, the saturation drain-source voltage is
determined by:




Figure 1: Drain Source saturation voltage

Where VT is the threshold voltage (V). For the triode region, the expression for the current is:

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