Oxford Cambridge and RSA
Tuesday 13 May 2025 – Afternoon
AS Level Computer Science
H046/01 Computing principles
Time allowed: 1 hour 15 minutes
Do not use:
* 9 8 8 2 5 4 4 7 0 3 *
• a calculator
* H 0 4 6 0 1 *
Please write clearly in black ink. Do not write in the barcodes.
Centre number Candidate number
First name(s)
Last name
INSTRUCTIONS
• Use black ink.
• Write your answer to each question in the space provided. You can use extra paper if
you need to, but you must clearly show your candidate number, the centre number and
the question numbers.
• Answer all the questions.
INFORMATION
• The total mark for this paper is 70.
• The marks for each question are shown in brackets [ ].
• Quality of extended response will be assessed in questions marked with an asterisk (*).
• This document has 16 pages.
ADVICE
• Read each question carefully before you start your answer.
© OCR 2025 [601/5030/0] OCR is an exempt Charity
DC (PQ/CGW) 324947/5 Turn over
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, 2
BLANK PAGE
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, 3
1 The table shows the steps of the Fetch stage only of the Fetch-Decode-Execute cycle. The
names of the registers are referred to as A, B, C and D.
1 The contents of the Register A are copied into the Register B.
2a RAM is read at the location specified by the Register B and its contents are copied into
the Register C.
2b Register A is incremented by 1.
3 The contents of the Register C are copied into the Register D.
(a) State the name of each register in the table.
Register A
Register B
Register C
Register D
[4]
(b) Describe how the performance of the Fetch-Decode-Execute cycle changes when increasing:
(i) The number of cores
..........................................................................................................................................................
..................................................................................................................................................... [1]
(ii) The clock speed
..........................................................................................................................................................
..................................................................................................................................................... [1]
© OCR 2025 Turn over
for more: tyrionpapers.com
Tuesday 13 May 2025 – Afternoon
AS Level Computer Science
H046/01 Computing principles
Time allowed: 1 hour 15 minutes
Do not use:
* 9 8 8 2 5 4 4 7 0 3 *
• a calculator
* H 0 4 6 0 1 *
Please write clearly in black ink. Do not write in the barcodes.
Centre number Candidate number
First name(s)
Last name
INSTRUCTIONS
• Use black ink.
• Write your answer to each question in the space provided. You can use extra paper if
you need to, but you must clearly show your candidate number, the centre number and
the question numbers.
• Answer all the questions.
INFORMATION
• The total mark for this paper is 70.
• The marks for each question are shown in brackets [ ].
• Quality of extended response will be assessed in questions marked with an asterisk (*).
• This document has 16 pages.
ADVICE
• Read each question carefully before you start your answer.
© OCR 2025 [601/5030/0] OCR is an exempt Charity
DC (PQ/CGW) 324947/5 Turn over
for more: tyrionpapers.com
, 2
BLANK PAGE
DO NOT WRITE ON THIS PAGE
© OCR 2025
for more: tyrionpapers.com
, 3
1 The table shows the steps of the Fetch stage only of the Fetch-Decode-Execute cycle. The
names of the registers are referred to as A, B, C and D.
1 The contents of the Register A are copied into the Register B.
2a RAM is read at the location specified by the Register B and its contents are copied into
the Register C.
2b Register A is incremented by 1.
3 The contents of the Register C are copied into the Register D.
(a) State the name of each register in the table.
Register A
Register B
Register C
Register D
[4]
(b) Describe how the performance of the Fetch-Decode-Execute cycle changes when increasing:
(i) The number of cores
..........................................................................................................................................................
..................................................................................................................................................... [1]
(ii) The clock speed
..........................................................................................................................................................
..................................................................................................................................................... [1]
© OCR 2025 Turn over
for more: tyrionpapers.com
