CI LI NH TH C
Digital Principles and
U23EC382 L T P J TW SL
Computer Organization 120 4
3 0 2 0 45 0
3.Syllabus: 45 + 30 = 75 Periods
Unit-I: Logic Gates and Minimization Techniques
(9)
Basic Theorems and properties of Boolean algebra – canonical form and standard
forms – digital logic gates – Minimization Techniques: K-Map (up to 4 variables)
– Don’t care condition - NAND & NOR Implementation.
Unit-II: Combinational Logic Circuits
(9)
Combinatorial Logic Circuits: Design Procedure – Half adder and Full adder –
Half Subtractor and Full Subtractor – Magnitude comparator – Encoder and
Decoder - Multiplexer and Demultiplexer – code converter (binary to gray, BCD
to excess-3 and vice versa)
Unit-III: Sequential Logic Circuits
(9)
Sequential Circuits: Flip-flops-Triggering of Flip-flops- Registers – Shift
Registers – Ripple Counters -Synchronous counters (up and down counter) –
Random Access Memory (RAM)
Unit-IV: Basic Computer Organization
(9)
Data Representation: Fixed and Floating Point – Micro operations: Arithmetic,
Logic, shift – Arithmetic Logic Shift Unit – Instruction Codes – Computer
registers – Computer Instructions – Timing and control – Instruction Cycle –
Design of Basic computer
Unit-V: Performance Enhancement Techniques
(9)
Parallel processing - Pipelining – Arithmetic and Instruction pipeline – RISC
pipeline - Memory hierarchy Main memory - Cache memory – Characteristics
and Multiprocessors – Interconnection Structures.
,
,
,
Digital Principles and
U23EC382 L T P J TW SL
Computer Organization 120 4
3 0 2 0 45 0
3.Syllabus: 45 + 30 = 75 Periods
Unit-I: Logic Gates and Minimization Techniques
(9)
Basic Theorems and properties of Boolean algebra – canonical form and standard
forms – digital logic gates – Minimization Techniques: K-Map (up to 4 variables)
– Don’t care condition - NAND & NOR Implementation.
Unit-II: Combinational Logic Circuits
(9)
Combinatorial Logic Circuits: Design Procedure – Half adder and Full adder –
Half Subtractor and Full Subtractor – Magnitude comparator – Encoder and
Decoder - Multiplexer and Demultiplexer – code converter (binary to gray, BCD
to excess-3 and vice versa)
Unit-III: Sequential Logic Circuits
(9)
Sequential Circuits: Flip-flops-Triggering of Flip-flops- Registers – Shift
Registers – Ripple Counters -Synchronous counters (up and down counter) –
Random Access Memory (RAM)
Unit-IV: Basic Computer Organization
(9)
Data Representation: Fixed and Floating Point – Micro operations: Arithmetic,
Logic, shift – Arithmetic Logic Shift Unit – Instruction Codes – Computer
registers – Computer Instructions – Timing and control – Instruction Cycle –
Design of Basic computer
Unit-V: Performance Enhancement Techniques
(9)
Parallel processing - Pipelining – Arithmetic and Instruction pipeline – RISC
pipeline - Memory hierarchy Main memory - Cache memory – Characteristics
and Multiprocessors – Interconnection Structures.
,
,
,
