ECEN 350 EXAM 1 QUESTIONS & ANSWERS
1. Moore's Law- answer - The number of transistors per square inch on integrated circuits doubles every year.
2. Computer processor cores directly execute the high-level code you write-
answer - False
3. A higher frequency processor will always have higher performance than a
lower frequency processor.- answer - False
4. An easy way to reduce the energy consumption needed to compute a given
job is to decrease its .- answer - Frequency, clock, or GHz
5. Decreasing response time should have no impact on throughput.- answer -
False
6. The processor directly executes the code you write in C, Java, C++, etc.- answer
- False
7. There is a one-to-one matching between lines of C and lines of an assembly
language.- answer - False
8. There is a one-to-one matching between lines of an assembly language and
lines of its machine language.- answer - True
9. The compiler will always produce better performing assembly than a human
can.- answer - False
10. Given the following mix of instruction classes and CPIs, calculate the
weight- ed average CPI for the program on a given CPU.
Class A- answer -
percentage- answer - 30%
CPI- answer - 2
Class B- answer -
percentage- answer - 20%
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,CPI- answer - 3
Class C- answer -
percentage- answer - 50%
CPI- answer - 1- answer - 1.7
11. Given two different computers A and B of the same ISA, running the same
application binary, what is the speedup of A over B?
A- answer - CPI = 1.5, Frequency = 2GHz
B- answer - CPI = 1, Frequency = 1.5GHz- answer -
CPUtimea = I*1.5/2GHz CPUtimeb = I*1/1.5GHz
Speedup a/b = 2G/1.5*1.5G = .8889
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, 12. Imagine you have converted a single threaded program to multi-threaded
so it can execute on a multi-core processor. You can support as many threads
as there are processors but there remains a 5% overhead which cannot be
parallelized. What is the maximum speedup you can expect with an infinite core
machine?- answer - 20x
13. is a good measure of the time a processor spent on a
given job.- answer - CPU time
14. ARMv8 and many other RISC ISAs are considered to be a "Load/Store Ar-
chitecture" because many computational instructions operate directly on the
memory.- answer - False. CISC instructions often operate directly on the memory, RISC instructions are load/store
because they must first move from memory with a separate load instruction, perform the computation and store back
with a store instruction.
15. Power increases dramatically with frequency because capacitance is increas-
ing with sucessive process technology generations.- answer - False. It is because voltage
must increase to achieve higher frequencies in a given process technology.
16. The wall was a primary driver of the transition to multi-
core processors.- answer - power
17. Translate the following assembly instruction to machine code in binary-
answer - SUB X0, X1, X2- answer - 11001011000000100000000000100000
18. Typical, ARMv8 R-Type arithmetic instructions have exactly
op
erands.-
- answer - 3
19. Which of the following is not a characteristic of the RISC philosophy?
1. Variable instruction length
2. Explicit load-store instructions
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1. Moore's Law- answer - The number of transistors per square inch on integrated circuits doubles every year.
2. Computer processor cores directly execute the high-level code you write-
answer - False
3. A higher frequency processor will always have higher performance than a
lower frequency processor.- answer - False
4. An easy way to reduce the energy consumption needed to compute a given
job is to decrease its .- answer - Frequency, clock, or GHz
5. Decreasing response time should have no impact on throughput.- answer -
False
6. The processor directly executes the code you write in C, Java, C++, etc.- answer
- False
7. There is a one-to-one matching between lines of C and lines of an assembly
language.- answer - False
8. There is a one-to-one matching between lines of an assembly language and
lines of its machine language.- answer - True
9. The compiler will always produce better performing assembly than a human
can.- answer - False
10. Given the following mix of instruction classes and CPIs, calculate the
weight- ed average CPI for the program on a given CPU.
Class A- answer -
percentage- answer - 30%
CPI- answer - 2
Class B- answer -
percentage- answer - 20%
1/
19
,CPI- answer - 3
Class C- answer -
percentage- answer - 50%
CPI- answer - 1- answer - 1.7
11. Given two different computers A and B of the same ISA, running the same
application binary, what is the speedup of A over B?
A- answer - CPI = 1.5, Frequency = 2GHz
B- answer - CPI = 1, Frequency = 1.5GHz- answer -
CPUtimea = I*1.5/2GHz CPUtimeb = I*1/1.5GHz
Speedup a/b = 2G/1.5*1.5G = .8889
2/
19
, 12. Imagine you have converted a single threaded program to multi-threaded
so it can execute on a multi-core processor. You can support as many threads
as there are processors but there remains a 5% overhead which cannot be
parallelized. What is the maximum speedup you can expect with an infinite core
machine?- answer - 20x
13. is a good measure of the time a processor spent on a
given job.- answer - CPU time
14. ARMv8 and many other RISC ISAs are considered to be a "Load/Store Ar-
chitecture" because many computational instructions operate directly on the
memory.- answer - False. CISC instructions often operate directly on the memory, RISC instructions are load/store
because they must first move from memory with a separate load instruction, perform the computation and store back
with a store instruction.
15. Power increases dramatically with frequency because capacitance is increas-
ing with sucessive process technology generations.- answer - False. It is because voltage
must increase to achieve higher frequencies in a given process technology.
16. The wall was a primary driver of the transition to multi-
core processors.- answer - power
17. Translate the following assembly instruction to machine code in binary-
answer - SUB X0, X1, X2- answer - 11001011000000100000000000100000
18. Typical, ARMv8 R-Type arithmetic instructions have exactly
op
erands.-
- answer - 3
19. Which of the following is not a characteristic of the RISC philosophy?
1. Variable instruction length
2. Explicit load-store instructions
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19
