Advanced Computer Architecture -
Exam 3
What are the 7 stages of the *instruction cycle*? - Answer-1. Fetch instruction
2. Decode instruction
3. Calculate operands
4. Fetch operands
5. Execute instruction
6. Write operand
7. (Optional) Handle interrupt
What is *pipelining*? - Answer-A technique for implementing instruction-level parallelism in a single
processor by splitting the instruction cycle up into various stages and executing each stage in parallel
*Figure 14.10*
What is the *cycle time* of an instruction pipeline? - Answer-The time needed to advance a set of
instructions *one stage* through the pipeline
What is the equation to calculate the *cycle time* of an instruction pipeline? - Answer-t = max[t_i] + d
max[t_i] is the slowest cycle time of all the stages of the pipeline
d is the time delay of the latch, needed to advance signals from one stage to the next
, An instruction pipeline has three stages: S1, S2, and S3. The cycle times of the stages are as follows:
t1 = 20
t2 = 40
t3 = 10
The time delay of the latch (d) is equal to 2.
*What is the cycle time of the entire instruction pipeline?* - Answer-max[t_i] + d
= max([20, 40, 10]) + 2
= 40 + 2
= 42
What is the equation for *the total amount of time required for a pipeline of k stages to execute n
instructions?* - Answer-T_k,n = [k + (n - 1)]t
k = the number of stages in the pipeline
n = the number of instructions to execute
t = the cycle time of the instruction pipeline
What is the equation for *the speedup of a processor with no pipelining versus a processor with
pipelining?* - Answer-S_k = (nk) / (k + n - 1)
What is a *pipeline hazard*? - Answer-When the pipeline, or some portion of the pipeline, must stall
because conditions do not permit continued execution
Exam 3
What are the 7 stages of the *instruction cycle*? - Answer-1. Fetch instruction
2. Decode instruction
3. Calculate operands
4. Fetch operands
5. Execute instruction
6. Write operand
7. (Optional) Handle interrupt
What is *pipelining*? - Answer-A technique for implementing instruction-level parallelism in a single
processor by splitting the instruction cycle up into various stages and executing each stage in parallel
*Figure 14.10*
What is the *cycle time* of an instruction pipeline? - Answer-The time needed to advance a set of
instructions *one stage* through the pipeline
What is the equation to calculate the *cycle time* of an instruction pipeline? - Answer-t = max[t_i] + d
max[t_i] is the slowest cycle time of all the stages of the pipeline
d is the time delay of the latch, needed to advance signals from one stage to the next
, An instruction pipeline has three stages: S1, S2, and S3. The cycle times of the stages are as follows:
t1 = 20
t2 = 40
t3 = 10
The time delay of the latch (d) is equal to 2.
*What is the cycle time of the entire instruction pipeline?* - Answer-max[t_i] + d
= max([20, 40, 10]) + 2
= 40 + 2
= 42
What is the equation for *the total amount of time required for a pipeline of k stages to execute n
instructions?* - Answer-T_k,n = [k + (n - 1)]t
k = the number of stages in the pipeline
n = the number of instructions to execute
t = the cycle time of the instruction pipeline
What is the equation for *the speedup of a processor with no pipelining versus a processor with
pipelining?* - Answer-S_k = (nk) / (k + n - 1)
What is a *pipeline hazard*? - Answer-When the pipeline, or some portion of the pipeline, must stall
because conditions do not permit continued execution
