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CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People

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CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People/CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People/CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People/CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People/CS 1104 AY T3 Unit 6 Discussion Assignment- University of the People

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3/12/2019 CS 1104 - AY2019-T3: Unit 6 Discussion Assignment


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Unit 6 Discussion Assignment
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Unit 6 Discussion Assignment
by Onyekwere Oluoha (Instructor) - Wednesday, 30 January 2019, 5:38 AM


For your discussion question response, please provide a response to each of the following
questions. Make sure that you include the question followed by your answer to the
question in your posting.

In the description of the Hack machine language in chapter 4, it is stated that in well-
written programs, a C-instruction that may cause a jump should not contain a reference
to M, and vice versa. Discuss why this should be avoided.
Research the concept of interrupts in a computer. You may want to look into how the
Z80 microprocessor handles interrupts. A good source of Z80 information is the Rodnay
Zaks book, "How to Program the Z80."



FYI, The Z80 8 bit microprocessor has been in production for forty years. Knowledge of the
Z80 is a great lead in for further study in more complicated machines.
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,3/12/2019 CS 1104 - AY2019-T3: Unit 6 Discussion Assignment

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Re: Unit 6 Discussion Assignment
by Benjamin Silverio Tubbs - Saturday, 9 March 2019, 6:28 AM


In the description of the Hack machine language in chapter 4, it is stated that in well-
written programs, a C-instruction that may cause a jump should not contain a
reference to M, and vice versa. Discuss why this should be avoided.


The Hack architecture consists of two 16 bit data registers. One is a data register called
D, and the other is an address register called A. The data register D can only be used to
store data, but the address register A can be used to store either data or addresses
(Nisan & Schocken, 2008). As the program is executing, the data in the A register will be
interpreted di erent based upon whether or not there is a jump.


There are two types of instructions that get sent between the A register and the CPU.
One is called an A instruction that will contain information about addresses which are
the locations of the data and instructions to be executed by the CPU (Nisan & Schocken,
2008). The other type are called compute instructions or C instructions. The C
instructions are much more complicated, but they simply contain information about
what operation to perform, where to store that information and whether or the system
would like to perform a jump (Nisan & Schocken, 2008).


The system chooses which operation to perform generally by simply incrementing to the
next instruction and performing the instructions in order. However, there are times
when some of the instructions are skipped over and the system proceeds from a new
part of the program. This is called a jump. The jump information is in the rightmost part
of a C instruction and is three bits long. When all three bits are set to zero, then the
system will never perform a jump under any conditions. When one or more of the bits is
set to one, then the system may perform a jump.


As mentioned above, there is a part of the C value that tells the computer where to store
the value. The value can be stored in one of three places: in D register, the A register, or
in the memory register that is addressed by A (referred to as M). As you can see this
cause could potentially cause a bit of problem.


https://my.uopeople.edu/mod/forum/discuss.php?d=191797 2/22

, 3/12/2019
If we have a jump, then we need interpret the instruction in A as an instruction to be
CS 1104 - AY2019-T3: Unit 6 Discussion Assignment

executed, but if the destination part of the memory is telling us to store the value in the
memory location referenced by A, then we we need to interpret the same value as the
address of a memory location, referred to as M.


Our issue is that the the value in M may be interpreted in at least two ways. As a RAM
memory location to store the value of the most recent calculation or as a Rom memory
location to which we need to jump. This is why we need to be very careful. When we
could be potentially jumping. If M contains a information about data or a RAM memory
location and we jump, this may cause us to jump to an incorrect address in the ROM
memory location.

Likewise if M contains information about a ROM memory location, it may accidentally be
interpreted as a memory location in RAM which would cause incorrect calculations or
values to be stored incorrectly in RAM. The way to solve this issue is to ensure that any
instruction that does not have the three jump bits set to 000 to have no reference to M.
And vice versa, any instruction that contains a reference to M ( nal bit of destination bits
1, for example, 001) should always have the nal three bits (jump bits) set to 000.


Research the concept of interrupts in a computer. You may want to look into how the
Z80 microprocessor handles interrupts. A good source of Z80 information is the Rodnay
Zaks book, "How to Program the Z80."


Everything we have talked about so far is how the CPU handles instructions that are
coming from a prewritten program like a ROM, but this is not the only type of instruction
that the CPU needs to be able to deal with. There are other instructions that the CPU
needs to be able to execute such as events from the user like a click or movement of the
mouse or a keystroke on a keyboard.


One way to deal with this would be for the CPU to periodically send signals to each of
these devices to check if the device has received an event. This technique is called
polling and has two huge drawbacks. One is that usually input devices are not being used
and as such it is a huge waste of CPU resources to be constantly polling them for event
handling (Whatis, 2016). The second issue is that the event will not be received until the
next poll which causes a huge amount of latency before the CPU gets to the event
(Whatis, 2016).




https://my.uopeople.edu/mod/forum/discuss.php?d=191797 3/22

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