Digital
Fundamentals
Tenth Edition
Floyd
Chapter 8
Synchronous
Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education,©Upper
2008 Pearson Education
Saddle River, NJ 07458. All Rights Reserved
, A 2-bit synchronous binary counter.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
, Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-
flops are assumed to be equal).
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
, Summary
Synchronous Counters
In a synchronous counter all flip-flops are clocked
together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J J1 J
has the same count 0 2
sequence as the 3-bit C C C
asynchronous counter K0 K1 K2
shown previously. CLK
The next slide shows how to analyze this counter by writing the logic
equations for each input. Notice the inputs to each flip-flop…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Fundamentals
Tenth Edition
Floyd
Chapter 8
Synchronous
Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education,©Upper
2008 Pearson Education
Saddle River, NJ 07458. All Rights Reserved
, A 2-bit synchronous binary counter.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
, Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-
flops are assumed to be equal).
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
, Summary
Synchronous Counters
In a synchronous counter all flip-flops are clocked
together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J J1 J
has the same count 0 2
sequence as the 3-bit C C C
asynchronous counter K0 K1 K2
shown previously. CLK
The next slide shows how to analyze this counter by writing the logic
equations for each input. Notice the inputs to each flip-flop…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
